test/CodeGen/X86/2011-12-15-vec_shift.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mattr=+sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-W-SSE4
; RUN: llc -mattr=-sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-WO-SSE4

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7"

; Test case for r146671
; With SSE41 - make sure operands to pblend are in the right order.
; Without SSE41 - make sure we're masking and pcmp'ing the VSELECT conditon vector.

define <16 x i8> @shift(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-W-SSE4-LABEL: shift:
; CHECK-W-SSE4:       ## %bb.0:
; CHECK-W-SSE4-NEXT:    movdqa %xmm0, %xmm2
; CHECK-W-SSE4-NEXT:    movdqa %xmm0, %xmm3
; CHECK-W-SSE4-NEXT:    psllw $4, %xmm3
; CHECK-W-SSE4-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-W-SSE4-NEXT:    psllw $5, %xmm1
; CHECK-W-SSE4-NEXT:    movdqa %xmm1, %xmm0
; CHECK-W-SSE4-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
; CHECK-W-SSE4-NEXT:    movdqa %xmm2, %xmm3
; CHECK-W-SSE4-NEXT:    paddb %xmm2, %xmm3
; CHECK-W-SSE4-NEXT:    paddb %xmm3, %xmm3
; CHECK-W-SSE4-NEXT:    paddb %xmm1, %xmm1
; CHECK-W-SSE4-NEXT:    movdqa %xmm1, %xmm0
; CHECK-W-SSE4-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
; CHECK-W-SSE4-NEXT:    movdqa %xmm2, %xmm3
; CHECK-W-SSE4-NEXT:    paddb %xmm2, %xmm3
; CHECK-W-SSE4-NEXT:    paddb %xmm1, %xmm1
; CHECK-W-SSE4-NEXT:    movdqa %xmm1, %xmm0
; CHECK-W-SSE4-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
; CHECK-W-SSE4-NEXT:    movdqa %xmm2, %xmm0
; CHECK-W-SSE4-NEXT:    retq
;
; CHECK-WO-SSE4-LABEL: shift:
; CHECK-WO-SSE4:       ## %bb.0:
; CHECK-WO-SSE4-NEXT:    psllw $5, %xmm1
; CHECK-WO-SSE4-NEXT:    pxor %xmm2, %xmm2
; CHECK-WO-SSE4-NEXT:    pxor %xmm3, %xmm3
; CHECK-WO-SSE4-NEXT:    pcmpgtb %xmm1, %xmm3
; CHECK-WO-SSE4-NEXT:    movdqa %xmm3, %xmm4
; CHECK-WO-SSE4-NEXT:    pandn %xmm0, %xmm4
; CHECK-WO-SSE4-NEXT:    psllw $4, %xmm0
; CHECK-WO-SSE4-NEXT:    pand %xmm3, %xmm0
; CHECK-WO-SSE4-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-WO-SSE4-NEXT:    por %xmm4, %xmm0
; CHECK-WO-SSE4-NEXT:    paddb %xmm1, %xmm1
; CHECK-WO-SSE4-NEXT:    pxor %xmm3, %xmm3
; CHECK-WO-SSE4-NEXT:    pcmpgtb %xmm1, %xmm3
; CHECK-WO-SSE4-NEXT:    movdqa %xmm3, %xmm4
; CHECK-WO-SSE4-NEXT:    pandn %xmm0, %xmm4
; CHECK-WO-SSE4-NEXT:    paddb %xmm0, %xmm0
; CHECK-WO-SSE4-NEXT:    paddb %xmm0, %xmm0
; CHECK-WO-SSE4-NEXT:    pand %xmm3, %xmm0
; CHECK-WO-SSE4-NEXT:    por %xmm4, %xmm0
; CHECK-WO-SSE4-NEXT:    paddb %xmm1, %xmm1
; CHECK-WO-SSE4-NEXT:    pcmpgtb %xmm1, %xmm2
; CHECK-WO-SSE4-NEXT:    movdqa %xmm2, %xmm1
; CHECK-WO-SSE4-NEXT:    pandn %xmm0, %xmm1
; CHECK-WO-SSE4-NEXT:    paddb %xmm0, %xmm0
; CHECK-WO-SSE4-NEXT:    pand %xmm2, %xmm0
; CHECK-WO-SSE4-NEXT:    por %xmm1, %xmm0
; CHECK-WO-SSE4-NEXT:    retq
  %1 = shl <16 x i8> %a, %b
  ret <16 x i8> %1
}