test/CodeGen/PowerPC/fp-classify-nan.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P8
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P9
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P8-NO-VSX

; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr8 < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P8
; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr9 < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P9
; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -mcpu=pwr8 -mattr=-vsx < %s \
; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=P8-NO-VSX
;
define zeroext i1 @test_is_nan_f64(double %x) #0 {
; P8-LABEL: test_is_nan_f64:
; P8:       # %bb.0:
; P8-NEXT:    xscmpudp cr0, f1, f1
; P8-NEXT:    li r3, 1
; P8-NEXT:    iseleq r3, 0, r3
; P8-NEXT:    blr
;
; P9-LABEL: test_is_nan_f64:
; P9:       # %bb.0:
; P9-NEXT:    xststdcdp cr0, f1, 64
; P9-NEXT:    li r3, 0
; P9-NEXT:    li r4, 1
; P9-NEXT:    iseleq r3, r4, r3
; P9-NEXT:    blr
;
; P8-NO-VSX-LABEL: test_is_nan_f64:
; P8-NO-VSX:       # %bb.0:
; P8-NO-VSX-NEXT:    fcmpu cr0, f1, f1
; P8-NO-VSX-NEXT:    li r3, 1
; P8-NO-VSX-NEXT:    iseleq r3, 0, r3
; P8-NO-VSX-NEXT:    blr
  %result = call i1 @llvm.is.fpclass.f64(double %x, i32 3)
  ret i1 %result
}

define zeroext i1 @test_is_not_nan_f64(double %x) #0 {
; P8-LABEL: test_is_not_nan_f64:
; P8:       # %bb.0:
; P8-NEXT:    xscmpudp cr0, f1, f1
; P8-NEXT:    li r3, 1
; P8-NEXT:    isel r3, 0, r3, un
; P8-NEXT:    blr
;
; P9-LABEL: test_is_not_nan_f64:
; P9:       # %bb.0:
; P9-NEXT:    xststdcdp cr0, f1, 64
; P9-NEXT:    li r3, 1
; P9-NEXT:    iseleq r3, 0, r3
; P9-NEXT:    blr
;
; P8-NO-VSX-LABEL: test_is_not_nan_f64:
; P8-NO-VSX:       # %bb.0:
; P8-NO-VSX-NEXT:    fcmpu cr0, f1, f1
; P8-NO-VSX-NEXT:    li r3, 1
; P8-NO-VSX-NEXT:    isel r3, 0, r3, un
; P8-NO-VSX-NEXT:    blr
  %result = call i1 @llvm.is.fpclass.f64(double %x, i32 1020)
  ret i1 %result
}

define zeroext i1 @test_is_nan_f32(float %x) #0 {
; P8-LABEL: test_is_nan_f32:
; P8:       # %bb.0:
; P8-NEXT:    xscmpudp cr0, f1, f1
; P8-NEXT:    li r3, 1
; P8-NEXT:    iseleq r3, 0, r3
; P8-NEXT:    blr
;
; P9-LABEL: test_is_nan_f32:
; P9:       # %bb.0:
; P9-NEXT:    xststdcsp cr0, f1, 64
; P9-NEXT:    li r3, 0
; P9-NEXT:    li r4, 1
; P9-NEXT:    iseleq r3, r4, r3
; P9-NEXT:    blr
;
; P8-NO-VSX-LABEL: test_is_nan_f32:
; P8-NO-VSX:       # %bb.0:
; P8-NO-VSX-NEXT:    fcmpu cr0, f1, f1
; P8-NO-VSX-NEXT:    li r3, 1
; P8-NO-VSX-NEXT:    iseleq r3, 0, r3
; P8-NO-VSX-NEXT:    blr
  %result = call i1 @llvm.is.fpclass.f32(float %x, i32 3)
  ret i1 %result
}

define zeroext i1 @test_is_not_nan_f32(float %x) #0 {
; P8-LABEL: test_is_not_nan_f32:
; P8:       # %bb.0:
; P8-NEXT:    xscmpudp cr0, f1, f1
; P8-NEXT:    li r3, 1
; P8-NEXT:    isel r3, 0, r3, un
; P8-NEXT:    blr
;
; P9-LABEL: test_is_not_nan_f32:
; P9:       # %bb.0:
; P9-NEXT:    xststdcsp cr0, f1, 64
; P9-NEXT:    li r3, 1
; P9-NEXT:    iseleq r3, 0, r3
; P9-NEXT:    blr
;
; P8-NO-VSX-LABEL: test_is_not_nan_f32:
; P8-NO-VSX:       # %bb.0:
; P8-NO-VSX-NEXT:    fcmpu cr0, f1, f1
; P8-NO-VSX-NEXT:    li r3, 1
; P8-NO-VSX-NEXT:    isel r3, 0, r3, un
; P8-NO-VSX-NEXT:    blr
  %result = call i1 @llvm.is.fpclass.f32(float %x, i32 1020)
  ret i1 %result
}

declare i1 @llvm.is.fpclass.f64(double, i32)
declare i1 @llvm.is.fpclass.f32(float, i32)
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
declare fp128 @llvm.fabs.f128(fp128)
declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
declare <2 x double> @llvm.fabs.v2f64(<2 x double>)

attributes #0 = {strictfp}