test/CodeGen/MIR/AMDGPU/target-flags.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
--- |
  define amdgpu_kernel void @flags() {
    ret void
  }

  declare void @foo()
...
---


name: flags
liveins:
  - { reg: '$sgpr0_sgpr1' }
frameInfo:
  maxAlignment:  8
registers:
  - { id: 0, class: sreg_64, preferred-register: '' }
  - { id: 1, class: sreg_64, preferred-register: '' }
body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: flags
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 12, implicit-def dead $scc
    ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @foo
    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @foo
    ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @foo
    ; CHECK-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-rel64) @foo
    ; CHECK-NEXT: [[S_MOV_B64_3:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel64) @foo
    ; CHECK-NEXT: S_ENDPGM 0
    %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 12, implicit-def dead $scc
    %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
    %2:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @foo
    %3:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @foo
    %4:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @foo
    %5:sreg_64 = S_MOV_B64 target-flags(amdgpu-rel64) @foo
    %6:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel64) @foo

    S_ENDPGM 0
...