test/CodeGen/ARM/lrint-conv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
;   %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
;   ret i32 %0
; }

define i32 @testmsws_builtin(float %x) {
; CHECK-LABEL: testmsws_builtin:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    b lrintf
entry:
  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
  ret i32 %0
}

define i32 @testmswd_builtin(double %x) {
; CHECK-LABEL: testmswd_builtin:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    b lrint
entry:
  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
  ret i32 %0
}

define i32 @testmswq_builtin(fp128 %x) {
; CHECK-LABEL: testmswq_builtin:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    .save {r11, lr}
; CHECK-NEXT:    push {r11, lr}
; CHECK-NEXT:    bl lrintl
; CHECK-NEXT:    pop {r11, pc}
entry:
  %0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x)
  ret i32 %0
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-FP16: {{.*}}
; CHECK-NOFP16: {{.*}}
; CHECK-SOFT: {{.*}}