| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 |
| ; RUN: llc < %s -mtriple=amdgpu9.00-amd-amdhsa | FileCheck %s |
| |
| ; Test llvm.convert.to.arbitrary.fp intrinsic expansion. |
| |
| declare i8 @llvm.convert.to.arbitrary.fp.i8.f32(float, metadata, metadata, i1) |
| declare i6 @llvm.convert.to.arbitrary.fp.i6.f32(float, metadata, metadata, i1) |
| declare i4 @llvm.convert.to.arbitrary.fp.i4.f32(float, metadata, metadata, i1) |
| declare <4 x i4> @llvm.convert.to.arbitrary.fp.v4i4.v4f32(<4 x float>, metadata, metadata, i1) |
| declare <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float>, metadata, metadata, i1) |
| declare <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float>, metadata, metadata, i1) |
| declare <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float>, metadata, metadata, i1) |
| declare <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f16(<2 x half>, metadata, metadata, i1) |
| |
| declare i8 @llvm.convert.to.arbitrary.fp.i8.f16(half, metadata, metadata, i1) |
| declare i8 @llvm.convert.to.arbitrary.fp.i8.bf16(bfloat, metadata, metadata, i1) |
| declare i8 @llvm.convert.to.arbitrary.fp.i8.f64(double, metadata, metadata, i1) |
| |
| ; Float8E5M2 |
| ; Layout: sign(1) exp(5) mant(2), bias=15 |
| ; Supports: Inf, NaN, signed zero, denormals |
| |
| ; Float8E5M2 runtime arg test |
| define i8 @to_f8e5m2_dynamic(float %x) { |
| ; CHECK-LABEL: to_f8e5m2_dynamic: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v4, 8, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v2, 0x7fffff, v1 |
| ; CHECK-NEXT: v_min_u32_e32 v4, 31, v4 |
| ; CHECK-NEXT: v_or_b32_e32 v2, 0x800000, v2 |
| ; CHECK-NEXT: v_sub_u32_e64 v6, v4, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v7, v2, 0, v6 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v4, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v7, v5, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v2, v2, v7 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v2, v5, v2 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v5, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v2, v5, v4, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v4, 0xfffff, v1 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v6, v1, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v4, v6, 1, v4 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v1, 20, v1 |
| ; CHECK-NEXT: v_and_b32_e32 v1, v1, v4 |
| ; CHECK-NEXT: v_add_u32_e32 v1, v6, v1 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, 14, v3, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v4, 2, v3 |
| ; CHECK-NEXT: v_or3_b32 v4, v5, v4, v1 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v1 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v3 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v3 |
| ; CHECK-NEXT: v_or_b32_e32 v1, 0x7c, v5 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x204 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v0, s4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret i8 %r |
| } |
| |
| ; Rounding mode tests |
| |
| ; Round toward zero with runtime arg |
| define i8 @to_f8e5m2_round_towardzero(float %x) { |
| ; CHECK-LABEL: to_f8e5m2_round_towardzero: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CHECK-NEXT: v_bfe_u32 v2, v1, 21, 2 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v4, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, 14, v4, vcc |
| ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffff, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v4, 8, v4 |
| ; CHECK-NEXT: v_or_b32_e32 v1, 0x800000, v1 |
| ; CHECK-NEXT: v_min_u32_e32 v4, 31, v4 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v1, v4, v1 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v1 |
| ; CHECK-NEXT: v_and_b32_sdwa v3, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v6, 2, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 4, vcc |
| ; CHECK-NEXT: v_or3_b32 v6, v3, v6, v2 |
| ; CHECK-NEXT: v_or3_b32 v1, v3, v4, v1 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v5 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v5 |
| ; CHECK-NEXT: v_or_b32_e32 v2, 0x7c, v3 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x204 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v0, s4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M2", metadata !"round.towardzero", i1 false) |
| ret i8 %r |
| } |
| |
| ; <4 x float> -> <4 x i4> Float4E2M1FN |
| define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) { |
| ; CHECK-LABEL: to_f4e2m1fn_v4f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 23, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v8, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v9, v5, 0, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v10, v7, v5 |
| ; CHECK-NEXT: v_and_or_b32 v9, v10, 1, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 28, v0 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 0x1fffff, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 2, vcc |
| ; CHECK-NEXT: v_and_b32_e32 v8, 8, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 21, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v4, v4, 22, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v9, v9, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v7, v7, v9 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v6, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v8, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 23, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v8, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v9, v5, 0, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v10, v7, v5 |
| ; CHECK-NEXT: v_and_or_b32 v9, v10, 1, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 28, v1 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 0x1fffff, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 2, vcc |
| ; CHECK-NEXT: v_and_b32_e32 v8, 8, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 21, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v4, v4, 22, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v9, v9, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v7, v7, v9 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v6, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v2 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 23, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v8, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v9, v5, 0, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v10, v7, v5 |
| ; CHECK-NEXT: v_and_or_b32 v9, v10, 1, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 28, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 0x1fffff, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 2, vcc |
| ; CHECK-NEXT: v_and_b32_e32 v8, 8, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 21, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v4, v4, 22, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v9, v9, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v7, v7, v9 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v6, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v8, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v3 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 23, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v8, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v9, v5, 0, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v10, v7, v5 |
| ; CHECK-NEXT: v_and_or_b32 v9, v10, 1, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 28, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 0x1fffff, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 2, vcc |
| ; CHECK-NEXT: v_and_b32_e32 v8, 8, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 21, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v4, v4, 22, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v9, v9, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v7, v7, v9 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v6, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <4 x i4> @llvm.convert.to.arbitrary.fp.v4i4.v4f32(<4 x float> %x, metadata !"Float4E2M1FN", metadata !"round.tonearest", i1 false) |
| ret <4 x i4> %r |
| } |
| |
| ; <2 x float> -> <2 x i8> Float8E5M2 |
| define <2 x i8> @to_f8e5m2_v2f32(<2 x float> %x) { |
| ; CHECK-LABEL: to_f8e5m2_v2f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v4, v1 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v5, 8, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffff, v2 |
| ; CHECK-NEXT: v_min_u32_e32 v5, 31, v5 |
| ; CHECK-NEXT: v_or_b32_e32 v3, 0x800000, v3 |
| ; CHECK-NEXT: v_sub_u32_e64 v7, v5, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v8, v3, 0, v7 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v5, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v8, v6, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, v7, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v3, v6, v3 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v3 |
| ; CHECK-NEXT: s_movk_i32 s6, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v6, v1, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v3, v6, v5, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0xfffff, v2 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v7, v2, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v5, v7, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 20, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v2, v2, v5 |
| ; CHECK-NEXT: v_add_u32_e32 v2, v7, v2 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v5, 2, v4 |
| ; CHECK-NEXT: v_or3_b32 v5, v6, v5, v2 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v4 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v4 |
| ; CHECK-NEXT: v_or_b32_e32 v2, 0x7c, v6 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 8, v6 |
| ; CHECK-NEXT: s_movk_i32 s7, 0x204 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v1, s7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v3, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0xfffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v4, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 20, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v9, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 14, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 2, v6 |
| ; CHECK-NEXT: v_or3_b32 v7, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v4 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v6 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v6 |
| ; CHECK-NEXT: v_or_b32_e32 v4, 0x7c, v8 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v0, s7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v2, 8, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; CHECK-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret <2 x i8> %r |
| } |
| |
| ; <2 x float> -> <2 x i8> Float8E4M3FN |
| define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) { |
| ; CHECK-LABEL: to_f8e4m3fn_v2f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v4, v1 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v5, 15, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffff, v2 |
| ; CHECK-NEXT: v_min_u32_e32 v5, 31, v5 |
| ; CHECK-NEXT: v_or_b32_e32 v3, 0x800000, v3 |
| ; CHECK-NEXT: v_sub_u32_e64 v7, v5, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v8, v3, 0, v7 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v5, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v8, v6, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, v7, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v3, v6, v3 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v6, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v3, v6, v5, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7ffff, v2 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v7, v2, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v5, v7, 1, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 19, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v2, v2, v5 |
| ; CHECK-NEXT: v_add_u32_e32 v2, v7, v2 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v4, vcc, 6, v4, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v5, 3, v4 |
| ; CHECK-NEXT: v_or3_b32 v2, v6, v5, v2 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_mov_b32_e32 v3, 0x7f |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0x7ffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v4, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v9, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 6, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v2, 8, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; CHECK-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false) |
| ret <2 x i8> %r |
| } |
| |
| ; <3 x float> -> <3 x i8> Float8E4M3FN |
| define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) { |
| ; CHECK-LABEL: to_f8e4m3fn_v3f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v5, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v6, 15, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffff, v3 |
| ; CHECK-NEXT: v_min_u32_e32 v6, 31, v6 |
| ; CHECK-NEXT: v_or_b32_e32 v4, 0x800000, v4 |
| ; CHECK-NEXT: v_sub_u32_e64 v8, v6, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v9, v4, 0, v8 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v7, v6, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v9, v7, 1, v9 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, v8, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v4, v7, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v7, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v4, v7, v6, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7ffff, v3 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v8, v3, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v6, v8, 1, v6 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 19, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v6 |
| ; CHECK-NEXT: v_add_u32_e32 v3, v8, v3 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, 6, v5, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v6, 3, v5 |
| ; CHECK-NEXT: v_or3_b32 v3, v7, v6, v3 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v4, 0x7f |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v3 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0x7ffff, v3 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v3, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 19, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v3, v9, v3 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 6, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v6 |
| ; CHECK-NEXT: v_or3_b32 v3, v8, v7, v3 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v2 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v3 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0x7ffff, v3 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v3, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 19, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v3, v9, v3 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 6, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v6 |
| ; CHECK-NEXT: v_or3_b32 v3, v8, v7, v3 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false) |
| ret <3 x i8> %r |
| } |
| |
| ; <4 x float> -> <4 x i8> Float8E4M3FN |
| define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) { |
| ; CHECK-LABEL: to_f8e4m3fn_v4f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0x7ffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v4, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v9, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 6, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v6 |
| ; CHECK-NEXT: v_or3_b32 v4, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v5, 0x7f |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v10, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7 |
| ; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v3 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v10, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7 |
| ; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v3, v3 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v2 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v10, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7 |
| ; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v3, 8, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v1, 8, v1 |
| ; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2 |
| ; CHECK-NEXT: v_lshl_or_b32 v1, v2, 16, v1 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v1, 8, v1 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3 |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false) |
| ret <4 x i8> %r |
| } |
| |
| ; <4 x float> -> <4 x i8> Float8E5M2 |
| define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) { |
| ; CHECK-LABEL: to_f8e5m2_v4f32: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v1 |
| ; CHECK-NEXT: v_sub_u32_e32 v7, 8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4 |
| ; CHECK-NEXT: v_min_u32_e32 v7, 31, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5 |
| ; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: s_movk_i32 s6, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v1, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v5, v8, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0xfffff, v4 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v9, v4, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v7, v9, 1, v7 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 20, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v7 |
| ; CHECK-NEXT: v_add_u32_e32 v4, v9, v4 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v6, vcc, 14, v6, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v7, 2, v6 |
| ; CHECK-NEXT: v_or3_b32 v7, v8, v7, v4 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v4 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v6 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v6 |
| ; CHECK-NEXT: v_or_b32_e32 v4, 0x7c, v8 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: s_movk_i32 s7, 0x204 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v1, s7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v4, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v0 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 8, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0xfffff, v5 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 20, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 14, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 2, v7 |
| ; CHECK-NEXT: v_or3_b32 v8, v9, v8, v5 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v7 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x7c, v9 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v0, s7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v3 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 8, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v3, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0xfffff, v5 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 20, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 14, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 2, v7 |
| ; CHECK-NEXT: v_or3_b32 v8, v9, v8, v5 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v7 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x7c, v9 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v3, s7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v3, v3 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v2 |
| ; CHECK-NEXT: v_sub_u32_e32 v8, 8, v7 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5 |
| ; CHECK-NEXT: v_min_u32_e32 v8, 31, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6 |
| ; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp |
| ; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v11 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v6, v9, v6 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v9, v2, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 0xfffff, v5 |
| ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_bfe_u32 v10, v5, 21, 2 |
| ; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 20, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v8 |
| ; CHECK-NEXT: v_add_u32_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 14, v7, vcc |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v8, 2, v7 |
| ; CHECK-NEXT: v_or3_b32 v8, v9, v8, v5 |
| ; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 3, v5 |
| ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 30, v7 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 30, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x7c, v9 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc |
| ; CHECK-NEXT: v_cmp_class_f32_e64 vcc, v2, s7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v3, 8, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v1, 8, v1 |
| ; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2 |
| ; CHECK-NEXT: v_lshl_or_b32 v1, v2, 16, v1 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v1, 8, v1 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3 |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret <4 x i8> %r |
| } |
| |
| ; <2 x half> -> <2 x i8> Float8E4M3FN |
| define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) { |
| ; CHECK-LABEL: to_f8e4m3fn_v2f16: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i16_f16_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u16_e32 v5, 2, v4 |
| ; CHECK-NEXT: v_min_u16_e32 v5, 15, v5 |
| ; CHECK-NEXT: v_frexp_mant_f16_e32 v1, v0 |
| ; CHECK-NEXT: v_sub_u16_e64 v8, v5, 1 clamp |
| ; CHECK-NEXT: v_and_b32_e32 v2, 0x3ff, v1 |
| ; CHECK-NEXT: v_lshlrev_b16_e64 v9, v8, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v3, 0x400, v2 |
| ; CHECK-NEXT: v_add_u16_e32 v9, -1, v9 |
| ; CHECK-NEXT: v_and_b32_e32 v9, v3, v9 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v6, v5, v3 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v7, v9, v7 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v3, v8, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v7 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v3, v6, v3 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v6, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_and_b32_e32 v7, 63, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v5, v6, v5 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v2, 7, v2 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_or_b32_e32 v3, v5, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 1, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v5, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v1, 6, v1 |
| ; CHECK-NEXT: v_and_b32_e32 v1, v1, v5 |
| ; CHECK-NEXT: v_add_u16_e32 v1, v2, v1 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v2, v4, v2 |
| ; CHECK-NEXT: v_add_u16_e32 v2, 6, v2 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v4, 3, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v4, v6, v4 |
| ; CHECK-NEXT: v_or_b32_e32 v1, v4, v1 |
| ; CHECK-NEXT: v_cmp_gt_i16_e32 vcc, 1, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; CHECK-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc |
| ; CHECK-NEXT: v_frexp_exp_i16_f16_sdwa v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 |
| ; CHECK-NEXT: v_sub_u16_e32 v7, 2, v6 |
| ; CHECK-NEXT: v_min_u16_e32 v7, 15, v7 |
| ; CHECK-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 |
| ; CHECK-NEXT: v_sub_u16_e64 v10, v7, 1 clamp |
| ; CHECK-NEXT: v_and_b32_e32 v4, 0x3ff, v3 |
| ; CHECK-NEXT: v_lshlrev_b16_e64 v11, v10, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v5, 0x400, v4 |
| ; CHECK-NEXT: v_add_u16_e32 v11, -1, v11 |
| ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7f |
| ; CHECK-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_and_b32_e32 v11, v5, v11 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v8, v7, v5 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 1, v8 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v9, v11, v9 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v5, v10, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v5, v5, v9 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v5, v8, v5 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v8, 7, v8 |
| ; CHECK-NEXT: v_and_b32_e32 v9, 63, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v7, v8, v7 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v4, 7, v4 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_or_b32_e32 v5, v7, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 1, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v7, v9, v7 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v3, 6, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v7 |
| ; CHECK-NEXT: v_add_u16_e32 v3, v4, v3 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v4, v6, v4 |
| ; CHECK-NEXT: v_add_u16_e32 v4, 6, v4 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v6, 3, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v6, v8, v6 |
| ; CHECK-NEXT: v_or_b32_e32 v3, v6, v3 |
| ; CHECK-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4 |
| ; CHECK-NEXT: v_mov_b32_e32 v4, 0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc |
| ; CHECK-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc |
| ; CHECK-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v0, 8, v2 |
| ; CHECK-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; CHECK-NEXT: v_and_b32_e32 v1, 0xff, v2 |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f16(<2 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false) |
| ret <2 x i8> %r |
| } |
| |
| ; Float8E5M2 from f16: half -> i8 |
| define i8 @to_f8e5m2_from_f16(half %x) { |
| ; CHECK-LABEL: to_f8e5m2_from_f16: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i16_f16_e32 v4, v0 |
| ; CHECK-NEXT: v_sub_u16_e32 v5, -5, v4 |
| ; CHECK-NEXT: v_min_u16_e32 v5, 15, v5 |
| ; CHECK-NEXT: v_frexp_mant_f16_e32 v1, v0 |
| ; CHECK-NEXT: v_sub_u16_e64 v8, v5, 1 clamp |
| ; CHECK-NEXT: v_and_b32_e32 v2, 0x3ff, v1 |
| ; CHECK-NEXT: v_lshlrev_b16_e64 v9, v8, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v3, 0x400, v2 |
| ; CHECK-NEXT: v_add_u16_e32 v9, -1, v9 |
| ; CHECK-NEXT: v_and_b32_e32 v9, v3, v9 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v6, v5, v3 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 1, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v7, v9, v7 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v3, v8, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v3, v3, v7 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v3, v6, v3 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v6, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v5, v6, v5 |
| ; CHECK-NEXT: v_and_b32_e32 v7, 0x7f, v1 |
| ; CHECK-NEXT: v_or_b32_e32 v3, v5, v3 |
| ; CHECK-NEXT: v_mov_b32_e32 v5, 1 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7 |
| ; CHECK-NEXT: v_and_b32_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v5, v7, v5 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v1, 7, v1 |
| ; CHECK-NEXT: v_and_b32_e32 v1, v1, v5 |
| ; CHECK-NEXT: v_add_u16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v2, v4, v2 |
| ; CHECK-NEXT: v_add_u16_e32 v2, 14, v2 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v4, 2, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v4, v6, v4 |
| ; CHECK-NEXT: v_or_b32_e32 v4, v4, v1 |
| ; CHECK-NEXT: v_cmp_gt_i16_e32 vcc, 1, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1 |
| ; CHECK-NEXT: v_cmp_eq_u16_e64 s[4:5], 30, v2 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 30, v2 |
| ; CHECK-NEXT: v_or_b32_e32 v1, 0x7c, v6 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc |
| ; CHECK-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x204 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc |
| ; CHECK-NEXT: v_cmp_class_f16_e64 vcc, v0, s4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f16(half %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret i8 %r |
| } |
| |
| ; Float8E5M2 from bf16: bfloat -> i8 |
| define i8 @to_f8e5m2_from_bf16(bfloat %x) { |
| ; CHECK-LABEL: to_f8e5m2_from_bf16: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v5, v1 |
| ; CHECK-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; CHECK-NEXT: s_movk_i32 s6, 0x7fff |
| ; CHECK-NEXT: v_sub_u16_e32 v6, -8, v5 |
| ; CHECK-NEXT: v_add3_u32 v3, v3, v2, s6 |
| ; CHECK-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; CHECK-NEXT: v_min_u16_e32 v6, 15, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc |
| ; CHECK-NEXT: s_movk_i32 s4, 0x7f |
| ; CHECK-NEXT: v_sub_u16_e64 v9, v6, 1 clamp |
| ; CHECK-NEXT: v_and_b32_sdwa v3, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_lshlrev_b16_e64 v10, v9, 1 |
| ; CHECK-NEXT: v_or_b32_e32 v4, 0x80, v3 |
| ; CHECK-NEXT: v_add_u16_e32 v10, -1, v10 |
| ; CHECK-NEXT: v_and_b32_e32 v10, v4, v10 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v7, v6, v4 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10 |
| ; CHECK-NEXT: v_and_b32_e32 v8, 1, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v8, v10, v8 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v4, v9, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v4, v4, v8 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v4, v7, v4 |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4 |
| ; CHECK-NEXT: v_mov_b32_e32 v8, 15 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 4, vcc |
| ; CHECK-NEXT: v_and_b32_sdwa v7, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v6, v7, v6 |
| ; CHECK-NEXT: v_lshrrev_b16_e32 v3, 5, v3 |
| ; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8 |
| ; CHECK-NEXT: v_or_b32_e32 v4, v6, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v6, 1, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v6, v8, v6 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 20, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v2, v2, v6 |
| ; CHECK-NEXT: v_add_u16_e32 v2, v3, v2 |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc |
| ; CHECK-NEXT: v_add_u16_e32 v3, v5, v3 |
| ; CHECK-NEXT: v_add_u16_e32 v3, 14, v3 |
| ; CHECK-NEXT: v_lshlrev_b16_e32 v5, 2, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v5, v7, v5 |
| ; CHECK-NEXT: v_or_b32_e32 v5, v5, v2 |
| ; CHECK-NEXT: v_cmp_gt_i16_e32 vcc, 1, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2 |
| ; CHECK-NEXT: v_cmp_eq_u16_e64 s[4:5], 30, v3 |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 30, v3 |
| ; CHECK-NEXT: v_or_b32_e32 v2, 0x7c, v7 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v2, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 |
| ; CHECK-NEXT: v_and_b32_sdwa v0, s6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; CHECK-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc |
| ; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, s4, v0 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc |
| ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7e |
| ; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call i8 @llvm.convert.to.arbitrary.fp.i8.bf16(bfloat %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret i8 %r |
| } |
| |
| ; Float8E5M2 from f64: double -> i8 |
| define i8 @to_f8e5m2_from_f64(double %x) { |
| ; CHECK-LABEL: to_f8e5m2_from_f64: |
| ; CHECK: ; %bb.0: |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1] |
| ; CHECK-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1] |
| ; CHECK-NEXT: s_movk_i32 s4, 0x80 |
| ; CHECK-NEXT: v_ashrrev_i32_e32 v13, 31, v12 |
| ; CHECK-NEXT: v_sub_co_u32_e32 v4, vcc, 37, v12 |
| ; CHECK-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v13, vcc |
| ; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5] |
| ; CHECK-NEXT: v_and_b32_e32 v15, 0xfffff, v3 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc |
| ; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 1, v[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v6, 1, v4, vcc |
| ; CHECK-NEXT: v_add_u32_e32 v14, -1, v6 |
| ; CHECK-NEXT: v_lshlrev_b64 v[6:7], v14, 1 |
| ; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, -1, v6 |
| ; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v7, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v7, 0x100000, v15 |
| ; CHECK-NEXT: v_mov_b32_e32 v6, v2 |
| ; CHECK-NEXT: v_and_b32_e32 v9, v7, v9 |
| ; CHECK-NEXT: v_and_b32_e32 v8, v2, v8 |
| ; CHECK-NEXT: v_lshrrev_b64 v[10:11], v4, v[6:7] |
| ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] |
| ; CHECK-NEXT: v_and_b32_e32 v9, 1, v10 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; CHECK-NEXT: v_lshrrev_b64 v[6:7], v14, v[6:7] |
| ; CHECK-NEXT: v_or_b32_e32 v7, v8, v9 |
| ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] |
| ; CHECK-NEXT: v_and_b32_e32 v6, v6, v7 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc |
| ; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, v10, v4 |
| ; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v11, vcc |
| ; CHECK-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5] |
| ; CHECK-NEXT: v_and_b32_sdwa v8, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc |
| ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc |
| ; CHECK-NEXT: v_or3_b32 v9, v8, v5, v4 |
| ; CHECK-NEXT: v_and_b32_e32 v5, 0x1ffff, v3 |
| ; CHECK-NEXT: v_mov_b32_e32 v4, v2 |
| ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] |
| ; CHECK-NEXT: v_bfe_u32 v4, v15, 18, 1 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc |
| ; CHECK-NEXT: v_or_b32_e32 v2, v2, v4 |
| ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 17, v3 |
| ; CHECK-NEXT: v_and_b32_e32 v2, v4, v2 |
| ; CHECK-NEXT: v_bfe_u32 v3, v3, 18, 2 |
| ; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 |
| ; CHECK-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc |
| ; CHECK-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[2:3] |
| ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc |
| ; CHECK-NEXT: v_add_co_u32_e64 v4, s[4:5], v12, v4 |
| ; CHECK-NEXT: v_addc_co_u32_e64 v5, s[4:5], 0, v13, s[4:5] |
| ; CHECK-NEXT: v_add_co_u32_e64 v4, s[4:5], 14, v4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc |
| ; CHECK-NEXT: v_addc_co_u32_e64 v5, s[4:5], 0, v5, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc |
| ; CHECK-NEXT: v_lshlrev_b64 v[6:7], 2, v[4:5] |
| ; CHECK-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[2:3] |
| ; CHECK-NEXT: v_cmp_eq_u64_e64 s[4:5], 30, v[4:5] |
| ; CHECK-NEXT: v_or_b32_e32 v6, v6, v8 |
| ; CHECK-NEXT: v_cmp_gt_i64_e64 s[6:7], 1, v[4:5] |
| ; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc |
| ; CHECK-NEXT: v_cmp_lt_i64_e32 vcc, 30, v[4:5] |
| ; CHECK-NEXT: v_or_b32_e32 v6, v6, v2 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v2, v6, v9, s[6:7] |
| ; CHECK-NEXT: v_or_b32_e32 v3, 0x7c, v8 |
| ; CHECK-NEXT: s_or_b64 vcc, vcc, s[4:5] |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc |
| ; CHECK-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1] |
| ; CHECK-NEXT: s_movk_i32 s4, 0x204 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc |
| ; CHECK-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], s4 |
| ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc |
| ; CHECK-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1] |
| ; CHECK-NEXT: v_mov_b32_e32 v3, 0x7e |
| ; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f64(double %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false) |
| ret i8 %r |
| } |
