test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=amdgpu9.50-amd-amdhsa | FileCheck -check-prefix=GFX950 %s
; RUN: llc < %s -mtriple=amdgpu11.70-amd-amdhsa | FileCheck -check-prefix=GFX1170 %s
; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa | FileCheck -check-prefix=GFX1250 %s

; llvm.convert.from.arbitrary.fp on FP8ConversionInsts targets with OCP FP8,
; plus E5M3FNU on GFX1250.

; Scalar Float8E5M2
define float @from_bf8_dynamic(i8 %x) {
; GFX950-LABEL: from_bf8_dynamic:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    v_cvt_f32_bf8_e32 v0, v0
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: from_bf8_dynamic:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_cvt_f32_bf8_e32 v0, v0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: from_bf8_dynamic:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_cvt_f32_bf8_e32 v0, v0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call float @llvm.convert.from.arbitrary.fp.f32.i8(i8 %x, metadata !"Float8E5M2")
  ret float %r
}

; Scalar Float8E4M3FN
define float @from_fp8_dynamic(i8 %x) {
; GFX950-LABEL: from_fp8_dynamic:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    v_cvt_f32_fp8_e32 v0, v0
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: from_fp8_dynamic:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_cvt_f32_fp8_e32 v0, v0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: from_fp8_dynamic:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_cvt_f32_fp8_e32 v0, v0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call float @llvm.convert.from.arbitrary.fp.f32.i8(i8 %x, metadata !"Float8E4M3FN")
  ret float %r
}

; v2f32
define <2 x float> @v2_from_bf8(<2 x i8> %x) {
; GFX950-LABEL: v2_from_bf8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v2_from_bf8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v2_from_bf8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <2 x float> @llvm.convert.from.arbitrary.fp.v2f32.v2i8(<2 x i8> %x, metadata !"Float8E5M2")
  ret <2 x float> %r
}

define <2 x float> @v2_from_fp8(<2 x i8> %x) {
; GFX950-LABEL: v2_from_fp8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v2_from_fp8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v2_from_fp8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <2 x float> @llvm.convert.from.arbitrary.fp.v2f32.v2i8(<2 x i8> %x, metadata !"Float8E4M3FN")
  ret <2 x float> %r
}

; v4f32
define <4 x float> @v4_from_bf8(<4 x i8> %x) {
; GFX950-LABEL: v4_from_bf8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_perm_b32 v2, v2, v3, s0
; GFX950-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX950-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v4_from_bf8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1170-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v4_from_bf8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1250-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <4 x float> @llvm.convert.from.arbitrary.fp.v4f32.v4i8(<4 x i8> %x, metadata !"Float8E5M2")
  ret <4 x float> %r
}

define <4 x float> @v4_from_fp8(<4 x i8> %x) {
; GFX950-LABEL: v4_from_fp8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_perm_b32 v2, v2, v3, s0
; GFX950-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX950-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v4_from_fp8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1170-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v4_from_fp8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1250-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <4 x float> @llvm.convert.from.arbitrary.fp.v4f32.v4i8(<4 x i8> %x, metadata !"Float8E4M3FN")
  ret <4 x float> %r
}

; v3f32
define <3 x float> @v3_from_bf8(<3 x i8> %x) {
; GFX950-LABEL: v3_from_bf8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX950-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX950-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v3_from_bf8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    v_and_b16 v2.l, 0xff, v2.l
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1170-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v3_from_bf8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    v_and_b16 v2.l, 0xff, v2.l
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_cvt_pk_f32_bf8_e32 v[0:1], v0
; GFX1250-NEXT:    v_cvt_pk_f32_bf8_e32 v[2:3], v2
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <3 x float> @llvm.convert.from.arbitrary.fp.v3f32.v3i8(<3 x i8> %x, metadata !"Float8E5M2")
  ret <3 x float> %r
}

define <3 x float> @v3_from_fp8(<3 x i8> %x) {
; GFX950-LABEL: v3_from_fp8:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    s_mov_b32 s0, 0xc0c0004
; GFX950-NEXT:    v_perm_b32 v0, v0, v1, s0
; GFX950-NEXT:    v_and_b32_e32 v2, 0xff, v2
; GFX950-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX950-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v3_from_fp8:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1170-NEXT:    v_and_b16 v2.l, 0xff, v2.l
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1170-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v3_from_fp8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX1250-NEXT:    v_and_b16 v2.l, 0xff, v2.l
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX1250-NEXT:    v_cvt_pk_f32_fp8_e32 v[2:3], v2
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <3 x float> @llvm.convert.from.arbitrary.fp.v3f32.v3i8(<3 x i8> %x, metadata !"Float8E4M3FN")
  ret <3 x float> %r
}

; E5M3FNU is selected by the clamp encoding bit on GFX1250.
define float @from_e5m3fnu_f32(i8 %x) {
; GFX950-LABEL: from_e5m3fnu_f32:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX950-NEXT:    v_and_b32_e32 v1, 7, v0
; GFX950-NEXT:    v_ffbh_u32_e32 v2, v1
; GFX950-NEXT:    v_sub_u32_e32 v3, 31, v2
; GFX950-NEXT:    v_lshlrev_b32_e64 v3, v3, 1
; GFX950-NEXT:    v_bitop3_b32 v3, v0, v3, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v4, -8, v2
; GFX950-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
; GFX950-NEXT:    v_sub_u32_e32 v2, 0x8d, v2
; GFX950-NEXT:    v_lshl_or_b32 v2, v2, 23, v3
; GFX950-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 20, v1
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v0
; GFX950-NEXT:    v_lshl_or_b32 v3, v0, 23, v3
; GFX950-NEXT:    v_add_u32_e32 v3, 0x38000000, v3
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX950-NEXT:    v_or_b32_e32 v3, v0, v1
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v0
; GFX950-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
; GFX950-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v1
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    s_nop 0
; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: from_e5m3fnu_f32:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_and_b32_e32 v1, 7, v0
; GFX1170-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX1170-NEXT:    v_clz_i32_u32_e32 v2, v1
; GFX1170-NEXT:    v_lshlrev_b32_e32 v5, 20, v1
; GFX1170-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
; GFX1170-NEXT:    v_sub_nc_u32_e32 v3, 31, v2
; GFX1170-NEXT:    v_add_nc_u32_e32 v4, -8, v2
; GFX1170-NEXT:    v_sub_nc_u32_e32 v2, 0x8d, v2
; GFX1170-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s0, 31, v0
; GFX1170-NEXT:    v_lshlrev_b32_e64 v3, v3, 1
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-NEXT:    v_xor_b32_e32 v3, v1, v3
; GFX1170-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
; GFX1170-NEXT:    v_lshl_or_b32 v4, v0, 23, v5
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_lshl_or_b32 v2, v2, 23, v3
; GFX1170-NEXT:    v_add_nc_u32_e32 v3, 0x38000000, v4
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1170-NEXT:    v_or_b32_e32 v4, v0, v1
; GFX1170-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 7, v1
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s1, 0, v4
; GFX1170-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1170-NEXT:    v_cndmask_b32_e64 v0, 0, v2, s1
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1170-NEXT:    v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: from_e5m3fnu_f32:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v0, v0 clamp
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call float @llvm.convert.from.arbitrary.fp.f32.i8(i8 %x, metadata !"Float8E5M3FNU")
  ret float %r
}

define <2 x float> @v2_from_e5m3fnu(<2 x i8> %x) {
; GFX950-LABEL: v2_from_e5m3fnu:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX950-NEXT:    v_and_b32_e32 v2, 7, v0
; GFX950-NEXT:    v_ffbh_u32_e32 v3, v2
; GFX950-NEXT:    v_sub_u32_e32 v4, 31, v3
; GFX950-NEXT:    v_lshlrev_b32_e64 v4, v4, 1
; GFX950-NEXT:    v_bitop3_b32 v4, v0, v4, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v5, -8, v3
; GFX950-NEXT:    v_lshlrev_b32_e32 v4, v5, v4
; GFX950-NEXT:    v_sub_u32_e32 v3, 0x8d, v3
; GFX950-NEXT:    v_lshl_or_b32 v3, v3, 23, v4
; GFX950-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 20, v2
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v0
; GFX950-NEXT:    v_lshl_or_b32 v4, v0, 23, v4
; GFX950-NEXT:    v_add_u32_e32 v4, 0x38000000, v4
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX950-NEXT:    v_or_b32_e32 v4, v0, v2
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v0
; GFX950-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; GFX950-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v2
; GFX950-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX950-NEXT:    v_and_b32_e32 v3, 7, v1
; GFX950-NEXT:    v_ffbh_u32_e32 v4, v3
; GFX950-NEXT:    v_sub_u32_e32 v5, 31, v4
; GFX950-NEXT:    v_lshlrev_b32_e64 v5, v5, 1
; GFX950-NEXT:    v_bitop3_b32 v5, v1, v5, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v6, -8, v4
; GFX950-NEXT:    v_lshlrev_b32_e32 v5, v6, v5
; GFX950-NEXT:    v_sub_u32_e32 v4, 0x8d, v4
; GFX950-NEXT:    v_lshl_or_b32 v4, v4, 23, v5
; GFX950-NEXT:    v_bfe_u32 v1, v1, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 20, v3
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
; GFX950-NEXT:    v_lshl_or_b32 v5, v1, 23, v5
; GFX950-NEXT:    v_add_u32_e32 v5, 0x38000000, v5
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX950-NEXT:    v_or_b32_e32 v5, v1, v3
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v1
; GFX950-NEXT:    s_nop 0
; GFX950-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v3
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    s_nop 0
; GFX950-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v2_from_e5m3fnu:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v1, v1.l
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_and_b32_e32 v2, 7, v0
; GFX1170-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX1170-NEXT:    v_clz_i32_u32_e32 v4, v2
; GFX1170-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1170-NEXT:    v_lshlrev_b32_e32 v5, 20, v2
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT:    v_or_b32_e32 v7, v0, v2
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s1, 7, v2
; GFX1170-NEXT:    v_sub_nc_u32_e32 v8, 31, v4
; GFX1170-NEXT:    v_add_nc_u32_e32 v11, -8, v4
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s2, 31, v0
; GFX1170-NEXT:    v_sub_nc_u32_e32 v4, 0x8d, v4
; GFX1170-NEXT:    v_lshlrev_b32_e64 v8, v8, 1
; GFX1170-NEXT:    v_lshl_or_b32 v0, v0, 23, v5
; GFX1170-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s0, 0, v7
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_xor_b32_e32 v2, v2, v8
; GFX1170-NEXT:    v_add_nc_u32_e32 v0, 0x38000000, v0
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-NEXT:    v_lshlrev_b32_e32 v2, v11, v2
; GFX1170-NEXT:    v_lshl_or_b32 v2, v4, 23, v2
; GFX1170-NEXT:    v_and_b32_e32 v3, 7, v1
; GFX1170-NEXT:    v_bfe_u32 v1, v1, 3, 5
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX1170-NEXT:    v_clz_i32_u32_e32 v6, v3
; GFX1170-NEXT:    v_lshlrev_b32_e32 v10, 20, v3
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s3, 0, v3
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s4, 0, v1
; GFX1170-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s0
; GFX1170-NEXT:    v_sub_nc_u32_e32 v9, 31, v6
; GFX1170-NEXT:    v_add_nc_u32_e32 v8, -8, v6
; GFX1170-NEXT:    v_sub_nc_u32_e32 v5, 0x8d, v6
; GFX1170-NEXT:    v_lshl_or_b32 v6, v1, 23, v10
; GFX1170-NEXT:    s_and_b32 vcc_lo, s4, s3
; GFX1170-NEXT:    v_lshlrev_b32_e64 v9, v9, 1
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s5, 7, v3
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_add_nc_u32_e32 v4, 0x38000000, v6
; GFX1170-NEXT:    v_xor_b32_e32 v9, v3, v9
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_lshlrev_b32_e32 v8, v8, v9
; GFX1170-NEXT:    v_or_b32_e32 v9, v1, v3
; GFX1170-NEXT:    v_lshl_or_b32 v5, v5, 23, v8
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s0, 0, v9
; GFX1170-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX1170-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 31, v1
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1170-NEXT:    v_cndmask_b32_e64 v1, 0, v2, s0
; GFX1170-NEXT:    s_and_b32 s0, s2, s1
; GFX1170-NEXT:    v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX1170-NEXT:    s_and_b32 s0, vcc_lo, s5
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1170-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v2_from_e5m3fnu:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v1, v0, v1, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v0, v1 clamp
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v1, v1 byte_sel:1 clamp
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <2 x float> @llvm.convert.from.arbitrary.fp.v2f32.v2i8(<2 x i8> %x, metadata !"Float8E5M3FNU")
  ret <2 x float> %r
}

define <4 x float> @v4_from_e5m3fnu(<4 x i8> %x) {
; GFX950-LABEL: v4_from_e5m3fnu:
; GFX950:       ; %bb.0:
; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT:    v_and_b32_e32 v0, 0xffff, v0
; GFX950-NEXT:    v_and_b32_e32 v4, 7, v0
; GFX950-NEXT:    v_ffbh_u32_e32 v5, v4
; GFX950-NEXT:    v_sub_u32_e32 v6, 31, v5
; GFX950-NEXT:    v_lshlrev_b32_e64 v6, v6, 1
; GFX950-NEXT:    v_bitop3_b32 v6, v0, v6, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v7, -8, v5
; GFX950-NEXT:    v_lshlrev_b32_e32 v6, v7, v6
; GFX950-NEXT:    v_sub_u32_e32 v5, 0x8d, v5
; GFX950-NEXT:    v_lshl_or_b32 v5, v5, 23, v6
; GFX950-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 20, v4
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v0
; GFX950-NEXT:    v_lshl_or_b32 v6, v0, 23, v6
; GFX950-NEXT:    v_add_u32_e32 v6, 0x38000000, v6
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX950-NEXT:    v_or_b32_e32 v6, v0, v4
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v0
; GFX950-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; GFX950-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v4
; GFX950-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX950-NEXT:    v_and_b32_e32 v5, 7, v1
; GFX950-NEXT:    v_ffbh_u32_e32 v6, v5
; GFX950-NEXT:    v_sub_u32_e32 v7, 31, v6
; GFX950-NEXT:    v_lshlrev_b32_e64 v7, v7, 1
; GFX950-NEXT:    v_bitop3_b32 v7, v1, v7, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v8, -8, v6
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, v8, v7
; GFX950-NEXT:    v_sub_u32_e32 v6, 0x8d, v6
; GFX950-NEXT:    v_lshl_or_b32 v6, v6, 23, v7
; GFX950-NEXT:    v_bfe_u32 v1, v1, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 20, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
; GFX950-NEXT:    v_lshl_or_b32 v7, v1, 23, v7
; GFX950-NEXT:    v_add_u32_e32 v7, 0x38000000, v7
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX950-NEXT:    v_or_b32_e32 v7, v1, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v1
; GFX950-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX950-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v5
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_and_b32_e32 v5, 7, v2
; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc
; GFX950-NEXT:    v_ffbh_u32_e32 v6, v5
; GFX950-NEXT:    v_sub_u32_e32 v7, 31, v6
; GFX950-NEXT:    v_lshlrev_b32_e64 v7, v7, 1
; GFX950-NEXT:    v_bitop3_b32 v7, v2, v7, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v8, -8, v6
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, v8, v7
; GFX950-NEXT:    v_sub_u32_e32 v6, 0x8d, v6
; GFX950-NEXT:    v_lshl_or_b32 v6, v6, 23, v7
; GFX950-NEXT:    v_bfe_u32 v2, v2, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 20, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
; GFX950-NEXT:    v_lshl_or_b32 v7, v2, 23, v7
; GFX950-NEXT:    v_add_u32_e32 v7, 0x38000000, v7
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX950-NEXT:    v_or_b32_e32 v7, v2, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v2
; GFX950-NEXT:    v_and_b32_e32 v3, 0xffff, v3
; GFX950-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v5
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_and_b32_e32 v5, 7, v3
; GFX950-NEXT:    v_cndmask_b32_e32 v2, v6, v4, vcc
; GFX950-NEXT:    v_ffbh_u32_e32 v6, v5
; GFX950-NEXT:    v_sub_u32_e32 v7, 31, v6
; GFX950-NEXT:    v_lshlrev_b32_e64 v7, v7, 1
; GFX950-NEXT:    v_bitop3_b32 v7, v3, v7, 7 bitop3:0x6c
; GFX950-NEXT:    v_add_u32_e32 v8, -8, v6
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, v8, v7
; GFX950-NEXT:    v_sub_u32_e32 v6, 0x8d, v6
; GFX950-NEXT:    v_lshl_or_b32 v6, v6, 23, v7
; GFX950-NEXT:    v_bfe_u32 v3, v3, 3, 5
; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 20, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX950-NEXT:    v_lshl_or_b32 v7, v3, 23, v7
; GFX950-NEXT:    v_add_u32_e32 v7, 0x38000000, v7
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX950-NEXT:    v_or_b32_e32 v7, v3, v5
; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT:    v_cmp_eq_u32_e64 s[0:1], 31, v3
; GFX950-NEXT:    s_nop 0
; GFX950-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v5
; GFX950-NEXT:    s_and_b64 vcc, s[0:1], vcc
; GFX950-NEXT:    s_nop 0
; GFX950-NEXT:    v_cndmask_b32_e32 v3, v6, v4, vcc
; GFX950-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: v4_from_e5m3fnu:
; GFX1170:       ; %bb.0:
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v0, v0.l
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v1, v1.l
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v2, v2.l
; GFX1170-NEXT:    v_cvt_u32_u16_e32 v3, v3.l
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1170-NEXT:    v_and_b32_e32 v4, 7, v0
; GFX1170-NEXT:    v_bfe_u32 v0, v0, 3, 5
; GFX1170-NEXT:    v_and_b32_e32 v6, 7, v2
; GFX1170-NEXT:    v_bfe_u32 v2, v2, 3, 5
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX1170-NEXT:    v_clz_i32_u32_e32 v8, v4
; GFX1170-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX1170-NEXT:    v_lshlrev_b32_e32 v9, 20, v4
; GFX1170-NEXT:    v_or_b32_e32 v10, v0, v4
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s1, 7, v4
; GFX1170-NEXT:    v_sub_nc_u32_e32 v11, 31, v8
; GFX1170-NEXT:    v_add_nc_u32_e32 v17, -8, v8
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s2, 31, v0
; GFX1170-NEXT:    v_sub_nc_u32_e32 v8, 0x8d, v8
; GFX1170-NEXT:    v_lshlrev_b32_e64 v11, v11, 1
; GFX1170-NEXT:    v_lshl_or_b32 v0, v0, 23, v9
; GFX1170-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
; GFX1170-NEXT:    v_clz_i32_u32_e32 v15, v6
; GFX1170-NEXT:    s_and_b32 s0, s2, s1
; GFX1170-NEXT:    v_xor_b32_e32 v4, v4, v11
; GFX1170-NEXT:    v_add_nc_u32_e32 v0, 0x38000000, v0
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s1, 0, v6
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s2, 0, v2
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_lshlrev_b32_e32 v4, v17, v4
; GFX1170-NEXT:    s_and_b32 s1, s2, s1
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s2, 31, v2
; GFX1170-NEXT:    v_lshl_or_b32 v4, v8, 23, v4
; GFX1170-NEXT:    v_and_b32_e32 v5, 7, v1
; GFX1170-NEXT:    v_bfe_u32 v1, v1, 3, 5
; GFX1170-NEXT:    v_sub_nc_u32_e32 v8, 31, v15
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX1170-NEXT:    v_clz_i32_u32_e32 v12, v5
; GFX1170-NEXT:    v_lshlrev_b32_e32 v13, 20, v5
; GFX1170-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX1170-NEXT:    v_and_b32_e32 v7, 7, v3
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s3, 0, v5
; GFX1170-NEXT:    v_sub_nc_u32_e32 v16, 31, v12
; GFX1170-NEXT:    v_add_nc_u32_e32 v9, -8, v12
; GFX1170-NEXT:    v_sub_nc_u32_e32 v12, 0x8d, v12
; GFX1170-NEXT:    v_lshl_or_b32 v13, v1, 23, v13
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s4, 0, v1
; GFX1170-NEXT:    v_lshlrev_b32_e64 v16, v16, 1
; GFX1170-NEXT:    v_or_b32_e32 v14, v1, v5
; GFX1170-NEXT:    v_lshlrev_b32_e64 v4, v8, 1
; GFX1170-NEXT:    v_add_nc_u32_e32 v8, 0x38000000, v13
; GFX1170-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX1170-NEXT:    v_xor_b32_e32 v16, v5, v16
; GFX1170-NEXT:    v_clz_i32_u32_e32 v11, v7
; GFX1170-NEXT:    s_and_b32 vcc_lo, s4, s3
; GFX1170-NEXT:    v_xor_b32_e32 v4, v6, v4
; GFX1170-NEXT:    v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX1170-NEXT:    v_lshlrev_b32_e32 v9, v9, v16
; GFX1170-NEXT:    v_sub_nc_u32_e32 v10, 31, v11
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s0, 31, v1
; GFX1170-NEXT:    v_bfe_u32 v3, v3, 3, 5
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s3, 0, v7
; GFX1170-NEXT:    v_lshl_or_b32 v9, v12, 23, v9
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s4, 0, v3
; GFX1170-NEXT:    v_dual_cndmask_b32 v8, v8, v9 :: v_dual_add_nc_u32 v9, -8, v15
; GFX1170-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_lshlrev_b32_e32 v4, v9, v4
; GFX1170-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc_lo
; GFX1170-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 7, v5
; GFX1170-NEXT:    v_lshlrev_b32_e64 v5, v10, 1
; GFX1170-NEXT:    v_sub_nc_u32_e32 v9, 0x8d, v15
; GFX1170-NEXT:    v_lshlrev_b32_e32 v10, 20, v6
; GFX1170-NEXT:    s_and_b32 s0, s0, vcc_lo
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX1170-NEXT:    v_xor_b32_e32 v1, v7, v5
; GFX1170-NEXT:    v_add_nc_u32_e32 v5, -8, v11
; GFX1170-NEXT:    v_lshl_or_b32 v4, v9, 23, v4
; GFX1170-NEXT:    v_lshl_or_b32 v9, v2, 23, v10
; GFX1170-NEXT:    v_lshlrev_b32_e32 v10, 20, v7
; GFX1170-NEXT:    v_lshlrev_b32_e32 v1, v5, v1
; GFX1170-NEXT:    v_sub_nc_u32_e32 v5, 0x8d, v11
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-NEXT:    v_add_nc_u32_e32 v9, 0x38000000, v9
; GFX1170-NEXT:    v_lshl_or_b32 v10, v3, 23, v10
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_lshl_or_b32 v1, v5, 23, v1
; GFX1170-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s1
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1170-NEXT:    v_add_nc_u32_e32 v5, 0x38000000, v10
; GFX1170-NEXT:    v_or_b32_e32 v10, v2, v6
; GFX1170-NEXT:    s_and_b32 s1, s4, s3
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s4, 31, v3
; GFX1170-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s1
; GFX1170-NEXT:    v_or_b32_e32 v5, v3, v7
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s1, 0, v10
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT:    v_cmp_ne_u32_e64 s3, 0, v5
; GFX1170-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s1
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s1, 7, v6
; GFX1170-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX1170-NEXT:    v_cndmask_b32_e64 v5, 0, v1, s3
; GFX1170-NEXT:    v_cmp_eq_u32_e64 s3, 7, v7
; GFX1170-NEXT:    v_cndmask_b32_e64 v1, v8, 0x7fc00000, s0
; GFX1170-NEXT:    s_and_b32 s0, s2, s1
; GFX1170-NEXT:    v_cndmask_b32_e64 v2, v4, 0x7fc00000, s0
; GFX1170-NEXT:    s_and_b32 s0, s4, s3
; GFX1170-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1170-NEXT:    v_cndmask_b32_e64 v3, v5, 0x7fc00000, s0
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v4_from_e5m3fnu:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_perm_b32 v1, v0, v1, 0xc0c0004
; GFX1250-NEXT:    v_perm_b32 v3, v2, v3, 0xc0c0004
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v0, v1 clamp
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v1, v1 byte_sel:1 clamp
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v2, v3 clamp
; GFX1250-NEXT:    v_cvt_f32_fp8_e64 v3, v3 byte_sel:1 clamp
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  %r = call <4 x float> @llvm.convert.from.arbitrary.fp.v4f32.v4i8(<4 x i8> %x, metadata !"Float8E5M3FNU")
  ret <4 x float> %r
}