test/CodeGen/AArch64/vector-interleave-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @aarch64_vector_interleave_idx_st2(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1) {
; CHECK-IAENABLED-LABEL: aarch64_vector_interleave_idx_st2:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    lsr x8, x1, #2
; CHECK-IAENABLED-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-IAENABLED-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-IAENABLED-NEXT:    add x8, x0, x8, lsl #4
; CHECK-IAENABLED-NEXT:    st2 { v0.4s, v1.4s }, [x8]
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: aarch64_vector_interleave_idx_st2:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    lsr x8, x1, #2
; CHECK-IADISABLED-NEXT:    zip2 v2.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    zip1 v0.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    add x8, x0, x8, lsl #4
; CHECK-IADISABLED-NEXT:    stp q0, q2, [x8]
; CHECK-IADISABLED-NEXT:    ret
entry:
  %idx1 = lshr i64 %idx, 2
  %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1

  %interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
  store <8 x float> %interleave, ptr %gep1, align 16
  ret void
}

define void @aarch64_vector_interleave_idx_st3(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1, <4 x float> %v2) {
; CHECK-LABEL: aarch64_vector_interleave_idx_st3:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    lsr x8, x1, #2
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2
; CHECK-NEXT:    add x8, x0, x8, lsl #4
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2
; CHECK-NEXT:    st3 { v0.4s, v1.4s, v2.4s }, [x8]
; CHECK-NEXT:    ret
entry:
  %idx1 = lshr i64 %idx, 2
  %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1

  %interleave = call <12 x float> @llvm.vector.interleave3.v12f32(<4 x float> %v0, <4 x float> %v1, <4 x float> %v2)
  store <12 x float> %interleave, ptr %gep1, align 16
  ret void
}

define void @aarch64_vector_interleave_idx_st4(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1, <4 x float> %v2, <4 x float> %v3) {
; CHECK-LABEL: aarch64_vector_interleave_idx_st4:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    lsr x8, x1, #2
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    add x8, x0, x8, lsl #4
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x8]
; CHECK-NEXT:    ret
entry:
  %idx1 = lshr i64 %idx, 2
  %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1

  %interleave = call <16 x float> @llvm.vector.interleave4.v16f32(<4 x float> %v0, <4 x float> %v1, <4 x float> %v2, <4 x float> %v3)
  store <16 x float> %interleave, ptr %gep1, align 16
  ret void
}