test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s

target triple = "aarch64-linux"

define void @mop4a_za16_fp8_1x1(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
; CHECK-LABEL: mop4a_za16_fp8_1x1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z24.d, z1.d
; CHECK-NEXT:    fmop4a za0.h, z0.b, z24.b
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
  ret void
}

define void @mop4a_za16_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
; CHECK-LABEL: mop4a_za16_fp8_1x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z25.d, z2.d
; CHECK-NEXT:    mov z24.d, z1.d
; CHECK-NEXT:    fmop4a za0.h, z0.b, { z24.b, z25.b }
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
  ret void
}

define void @mop4a_za16_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
; CHECK-LABEL: mop4a_za16_fp8_2x1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z24.d, z2.d
; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    fmop4a za0.h, { z0.b, z1.b }, z24.b
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
  ret void
}

define void @mop4a_za16_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
; CHECK-LABEL: mop4a_za16_fp8_2x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z25.d, z3.d
; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    mov z24.d, z2.d
; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    fmop4a za0.h, { z0.b, z1.b }, { z24.b, z25.b }
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
  ret void
}

define void @mop4a_za32_fp8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
; CHECK-LABEL: mop4a_za32_fp8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z24.d, z1.d
; CHECK-NEXT:    fmop4a za0.s, z0.b, z24.b
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
  ret void
}

define void @mop4a_za32_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
; CHECK-LABEL: mop4a_za32_fp8_1x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z25.d, z2.d
; CHECK-NEXT:    mov z24.d, z1.d
; CHECK-NEXT:    fmop4a za0.s, z0.b, { z24.b, z25.b }
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
  ret void
}

define void @mop4a_za32_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
; CHECK-LABEL: mop4a_za32_fp8_2x1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z24.d, z2.d
; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    fmop4a za0.s, { z0.b, z1.b }, z24.b
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
  ret void
}

define void @mop4a_za32_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
; CHECK-LABEL: mop4a_za32_fp8_2x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z25.d, z3.d
; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    mov z24.d, z2.d
; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
; CHECK-NEXT:    fmop4a za0.s, { z0.b, z1.b }, { z24.b, z25.b }
; CHECK-NEXT:    ret
  call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
  ret void
}

attributes #0 = {nounwind "target-features" = "+sme-f8f16,+sme-f8f32,+sme2p1,+sme-mop4" }