test/CodeGen/AArch64/shl-to-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o - | FileCheck %s

define <16 x i8> @shl_v16i8(<16 x i8> %a) {
; CHECK-LABEL: shl_v16i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
; CHECK-NEXT:    ret
entry:
  %add.i = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  ret <16 x i8> %add.i
}

define <8 x i16> @shl_v8i16(<8 x i16> %a) {
; CHECK-LABEL: shl_v8i16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
; CHECK-NEXT:    ret
entry:
  %add.i = shl <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
  ret <8 x i16> %add.i
}

define <4 x i32> @shl_v4i32(<4 x i32> %a) {
; CHECK-LABEL: shl_v4i32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
; CHECK-NEXT:    ret
entry:
  %add.i = shl <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
  ret <4 x i32> %add.i
}

define <2 x i64> @shl_v2i64(<2 x i64> %a) {
; CHECK-LABEL: shl_v2i64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
; CHECK-NEXT:    ret
entry:
  %add.i = shl <2 x i64> %a, <i64 1, i64 1>
  ret <2 x i64> %add.i
}

define <8 x i8> @shl_v8i8(<8 x i8> %a) {
; CHECK-LABEL: shl_v8i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.8b, v0.8b, v0.8b
; CHECK-NEXT:    ret
entry:
  %add.i = shl <8 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  ret <8 x i8> %add.i
}

define <4 x i16> @shl_v4i16(<4 x i16> %a) {
; CHECK-LABEL: shl_v4i16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.4h, v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %add.i = shl <4 x i16> %a, <i16 1, i16 1, i16 1, i16 1>
  ret <4 x i16> %add.i
}

define <2 x i32> @shl_v2i32(<2 x i32> %a) {
; CHECK-LABEL: shl_v2i32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    add v0.2s, v0.2s, v0.2s
; CHECK-NEXT:    ret
entry:
  %add.i = shl <2 x i32> %a, <i32 1, i32 1>
  ret <2 x i32> %add.i
}

define <8 x i16> @sshll_v8i8(<8 x i8> %a) {
; CHECK-LABEL: sshll_v8i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sshll v0.8h, v0.8b, #1
; CHECK-NEXT:    ret
  %1 = sext <8 x i8> %a to <8 x i16>
  %tmp = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
  ret <8 x i16> %tmp
}

define <4 x i32> @sshll_v4i16(<4 x i16> %a) {
; CHECK-LABEL: sshll_v4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sshll v0.4s, v0.4h, #1
; CHECK-NEXT:    ret
  %1 = sext <4 x i16> %a to <4 x i32>
  %tmp = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
  ret <4 x i32> %tmp
}

define <2 x i64> @sshll_v2i32(<2 x i32> %a) {
; CHECK-LABEL: sshll_v2i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sshll v0.2d, v0.2s, #1
; CHECK-NEXT:    ret
  %1 = sext <2 x i32> %a to <2 x i64>
  %tmp = shl <2 x i64> %1, <i64 1, i64 1>
  ret <2 x i64> %tmp
}

define <8 x i16> @ushll_v8i8(<8 x i8> %a) {
; CHECK-LABEL: ushll_v8i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ushll v0.8h, v0.8b, #1
; CHECK-NEXT:    ret
  %1 = zext <8 x i8> %a to <8 x i16>
  %tmp = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
  ret <8 x i16> %tmp
}

define <4 x i32> @ushll_v4i16(<4 x i16> %a) {
; CHECK-LABEL: ushll_v4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ushll v0.4s, v0.4h, #1
; CHECK-NEXT:    ret
  %1 = zext <4 x i16> %a to <4 x i32>
  %tmp = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
  ret <4 x i32> %tmp
}

define <2 x i64> @ushll_v2i32(<2 x i32> %a) {
; CHECK-LABEL: ushll_v2i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ushll v0.2d, v0.2s, #1
; CHECK-NEXT:    ret
  %1 = zext <2 x i32> %a to <2 x i64>
  %tmp = shl <2 x i64> %1, <i64 1, i64 1>
  ret <2 x i64> %tmp
}