| # REQUIRES: asserts |
| |
| # RUN: llc -filetype=null %s -mtriple=aarch64-unknown -mattr=+arith-cbz-fusion -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s |
| # RUN: llc -filetype=null %s -mtriple=aarch64-unknown -mcpu=cyclone -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s |
| # RUN: llc -filetype=null %s -mtriple=aarch64-unknown -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s |
| |
| # CHECK-LABEL: addwri_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: addwri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwri_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: addwri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| # CHECK-LABEL: addwri_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: addwri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwri_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: addwri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: addwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: addwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: addwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: addwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: addwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: addwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: addwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: addwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_addwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_addwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ADDWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwri_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: andwri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwri_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: andwri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwri_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: andwri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwri_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: andwri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: andwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: andwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: andwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: andwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: andwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: andwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: andwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: andwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_andwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_andwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ANDWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwri_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: eorwri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwri_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: eorwri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwri_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: eorwri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwri_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: eorwri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: eorwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: eorwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: eorwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: eorwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: eorwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: eorwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: eorwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: eorwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_eorwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_eorwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = EORWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: ornwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: ornwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: ornwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: ornwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: ornwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: ornwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: ornwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: ornwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_ornwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_ornwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORNWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwri_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: orrwri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwri_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: orrwri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwri_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: orrwri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwri_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: orrwri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWri $w0, 4096 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: orrwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: orrwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: orrwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: orrwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: orrwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: orrwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: orrwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: orrwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_orrwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_orrwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = ORRWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwri_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: subwri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwri_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: subwri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwri_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: subwri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwri_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: subwri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWri $w0, 13, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: subwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: subwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: subwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: subwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: subwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: subwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: subwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: subwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_subwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_subwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = SUBWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrr_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: bicwrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: bicwrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrr_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: bicwrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: bicwrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrr $w0, $w1 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrs_cbz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZW |
| --- |
| name: bicwrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: bicwrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrs_tbz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZW |
| --- |
| name: bicwrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicwrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZW |
| --- |
| name: bicwrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrs $w0, $w1, 0 |
| $w3 = ORRWri $w2, 4096 |
| TBNZW $w0, 8, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_bicwrs |
| # CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZW |
| --- |
| name: no_fuse_positive_shift_bicwrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $w0, $w1, $w2 |
| $w0 = BICWrs $w0, $w1, 12 |
| $w3 = ORRWri $w2, 4096 |
| CBNZW $w0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxri_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: addxri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxri_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: addxri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxri_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: addxri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxri_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: addxri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: addxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: addxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: addxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: addxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: addxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: addxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: addxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: addxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: addxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_addxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_addxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ADDXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxri_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: andxri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxri_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: andxri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxri_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: andxri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxri_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: andxri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: andxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: andxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: andxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: andxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: andxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: andxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: andxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: andxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: andxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_andxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_andxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ANDXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxri_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: eorxri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxri_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: eorxri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxri_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: eorxri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxri_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: eorxri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: eorxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: eorxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: eorxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: eorxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: eorxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: eorxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: eorxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: eorxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: eorxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_eorxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_eorxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = EORXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: ornxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: ornxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: ornxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: ornxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: ornxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: ornxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: ornxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: ornxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: ornxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_ornxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_ornxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORNXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxri_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: orrxri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxri_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: orrxri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxri_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: orrxri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxri_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: orrxri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXri $x0, 8192 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: orrxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: orrxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: orrxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: orrxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: orrxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: orrxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: orrxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: orrxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: orrxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_orrxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_orrxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = ORRXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxri_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: subxri_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxri_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: subxri_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxri_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: subxri_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxri_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: subxri_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXri $x0, 13, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: subxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: subxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: subxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: subxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: subxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: subxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: subxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: subxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: subxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_subxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_subxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = SUBXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrr_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: bicxrr_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrr_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: bicxrr_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrr_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: bicxrr_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrr_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: bicxrr_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrr $x0, $x1 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrs_cbz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBZX |
| --- |
| name: bicxrs_cbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrs_cbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: bicxrs_cbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrs_tbz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBZX |
| --- |
| name: bicxrs_tbz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: bicxrs_tbnz |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0 |
| # CHECK: Successors: |
| # CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: TBNZX |
| --- |
| name: bicxrs_tbnz |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrs $x0, $x1, 0 |
| $x3 = ORRXri $x2, 8192 |
| TBNZX $x0, 32, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
| |
| # CHECK-LABEL: no_fuse_positive_shift_bicxrs |
| # CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 12 |
| # CHECK: Successors: |
| # CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster |
| # CHECK: ExitSU: CBNZX |
| --- |
| name: no_fuse_positive_shift_bicxrs |
| tracksRegLiveness: true |
| isSSA: false |
| noVRegs: true |
| body: | |
| bb.0: |
| successors: %bb.1, %bb.2 |
| liveins: $x0, $x1, $x2 |
| $x0 = BICXrs $x0, $x1, 12 |
| $x3 = ORRXri $x2, 8192 |
| CBNZX $x0, %bb.2 |
| bb.1: |
| RET undef $lr |
| bb.2: |
| RET undef $lr |
| ... |
