test/CodeGen/AArch64/inlineasm-Uc-constraint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -o - | FileCheck %s

target triple = "arm64-none-linux-gnu"

define void @test_constraints_Uci_w(i32 %a) {
; CHECK-LABEL: test_constraints_Uci_w:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, w0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x8
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i32 %a)
  ret void
}

; As test_constraints_Uci_w but ensures non-legal types are also covered.
define void @test_constraints_Uci_w_i8(i8 %a) {
; CHECK-LABEL: test_constraints_Uci_w_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, w0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x8
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i8 %a)
  ret void
}

define void @test_constraints_Uci_x(i64 %a) {
; CHECK-LABEL: test_constraints_Uci_x:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x8
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i64 %a)
  ret void
}

define void @test_constraint_Ucj_w(i32 %a) {
; CHECK-LABEL: test_constraint_Ucj_w:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w12, w0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x12
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i32 %a)
  ret void
}

; As test_constraints_Ucj_w but ensures non-legal types are also covered.
define void @test_constraint_Ucj_w_i8(i8 %a) {
; CHECK-LABEL: test_constraint_Ucj_w_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w12, w0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x12
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i8 %a)
  ret void
}

define void @test_constraint_Ucj_x(i64 %a) {
; CHECK-LABEL: test_constraint_Ucj_x:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x12, x0
; CHECK-NEXT:    //APP
; CHECK-NEXT:    add x0, x0, x12
; CHECK-NEXT:    //NO_APP
; CHECK-NEXT:    ret
  call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i64 %a)
  ret void
}