test/CodeGen/AArch64/cmpbr-branch-relaxation.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=3 \
# RUN:    -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
# RUN:    FileCheck -check-prefix=RELAX %s
# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=9 \
# RUN:    -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
# RUN:    FileCheck -check-prefix=NO-RELAX %s
---
name:            relax_cb
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
body:             |
  ; RELAX-LABEL: name: relax_cb
  ; RELAX: bb.0:
  ; RELAX-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; RELAX-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; RELAX-NEXT:   CBWPrr 1, [[COPY]], [[COPY1]], %bb.1
  ; RELAX-NEXT:   B %bb.2
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT: bb.1:
  ; RELAX-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; RELAX-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
  ; RELAX-NEXT:   [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
  ; RELAX-NEXT:   [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
  ; RELAX-NEXT:   [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
  ; RELAX-NEXT:   $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT: bb.2:
  ; RELAX-NEXT:   RET_ReallyLR implicit $w0
  ;
  ; NO-RELAX-LABEL: name: relax_cb
  ; NO-RELAX: bb.0:
  ; NO-RELAX-NEXT:   successors: %bb.1, %bb.2
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; NO-RELAX-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; NO-RELAX-NEXT:   CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT: bb.1:
  ; NO-RELAX-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; NO-RELAX-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
  ; NO-RELAX-NEXT:   [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
  ; NO-RELAX-NEXT:   [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
  ; NO-RELAX-NEXT:   [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
  ; NO-RELAX-NEXT:   $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT: bb.2:
  ; NO-RELAX-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBWPrr 0, %0, %1, %bb.2

  bb.1:
    successors: %bb.2
    %2:gpr32 = ADDWrr %0, %1
    %3:gpr32 = ADDWrr %2, %1
    %4:gpr32 = ADDWrr %3, %2
    %5:gpr32 = ADDWrr %4, %3
    %6:gpr32 = ADDWrr %5, %4
    $w0 = ADDWrr %6, %5

  bb.2:
    RET_ReallyLR implicit $w0
...
---
name:              relax_and_split_block
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
body:             |
  ; RELAX-LABEL: name: relax_and_split_block
  ; RELAX: bb.0:
  ; RELAX-NEXT:   liveins: $w0, $w1
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; RELAX-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; RELAX-NEXT:   CBWPrr 1, [[COPY]], [[COPY1]], %bb.3
  ; RELAX-NEXT:   B %bb.2
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT: bb.3:
  ; RELAX-NEXT:   liveins: $w0, $w1
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT:   CBWPrr 0, [[COPY]], [[COPY1]], %bb.1
  ; RELAX-NEXT:   B %bb.2
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT: bb.1:
  ; RELAX-NEXT:   liveins: $w0, $w1
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; RELAX-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
  ; RELAX-NEXT:   [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
  ; RELAX-NEXT:   [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
  ; RELAX-NEXT:   [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
  ; RELAX-NEXT:   $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT: bb.2:
  ; RELAX-NEXT:   liveins: $w0, $w1
  ; RELAX-NEXT: {{  $}}
  ; RELAX-NEXT:   RET_ReallyLR implicit $w0
  ;
  ; NO-RELAX-LABEL: name: relax_and_split_block
  ; NO-RELAX: bb.0:
  ; NO-RELAX-NEXT:   successors: %bb.1, %bb.2
  ; NO-RELAX-NEXT:   liveins: $w0, $w1
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; NO-RELAX-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; NO-RELAX-NEXT:   CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
  ; NO-RELAX-NEXT:   CBWPrr 1, [[COPY]], [[COPY1]], %bb.2
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT: bb.1:
  ; NO-RELAX-NEXT:   liveins: $w0, $w1
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; NO-RELAX-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
  ; NO-RELAX-NEXT:   [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
  ; NO-RELAX-NEXT:   [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
  ; NO-RELAX-NEXT:   [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
  ; NO-RELAX-NEXT:   $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT: bb.2:
  ; NO-RELAX-NEXT:   liveins: $w0, $w1
  ; NO-RELAX-NEXT: {{  $}}
  ; NO-RELAX-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1
    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBWPrr 0, %0, %1, %bb.2
    CBWPrr 1, %0, %1, %bb.2

  bb.1:
    successors: %bb.2
    liveins: $w0, $w1
    %2:gpr32 = ADDWrr %0, %1
    %3:gpr32 = ADDWrr %2, %1
    %4:gpr32 = ADDWrr %3, %2
    %5:gpr32 = ADDWrr %4, %3
    %6:gpr32 = ADDWrr %5, %4
    $w0 = ADDWrr %6, %5

  bb.2:
    liveins: $w0, $w1
    RET_ReallyLR implicit $w0
...