test/CodeGen/AArch64/GlobalISel/select-int-ext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @anyext_s64_from_s32() { ret void }
  define void @anyext_s32_from_s8() { ret void }
  define void @anyext_v8s16_from_v8s8() { ret void }
  define void @anyext_v4s32_from_v4s16() { ret void }
  define void @anyext_v2s64_from_v2s32() { ret void }

  define void @zext_s64_from_s32() { ret void }
  define void @zext_s32_from_s16() { ret void }
  define void @zext_s32_from_s8() { ret void }
  define void @zext_s16_from_s8() { ret void }
  define void @zext_v8s16_from_v8s8() { ret void }
  define void @zext_v4s32_from_v4s16() { ret void }
  define void @zext_v2s64_from_v2s32() { ret void }

  define void @sext_s64_from_s32() { ret void }
  define void @sext_s32_from_s16() { ret void }
  define void @sext_s32_from_s8() { ret void }
  define void @sext_s16_from_s8() { ret void }
  define void @sext_v8s16_from_v8s8() { ret void }
  define void @sext_v4s32_from_v4s16() { ret void }
  define void @sext_v2s64_from_v2s32() { ret void }
...

---
name:            anyext_s64_from_s32
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: anyext_s64_from_s32
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
    ; CHECK-NEXT: $x0 = COPY [[INSERT_SUBREG]]
    %0(i32) = COPY $w0
    %1(i64) = G_ANYEXT %0
    $x0 = COPY %1(i64)
...

---
name:            anyext_s32_from_s8
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: anyext_s32_from_s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
    %2:gpr(i32) = COPY $w0
    %0(i8) = G_TRUNC %2
    %1(i32) = G_ANYEXT %0
    $w0 = COPY %1(i32)
...

---
name:            anyext_v8s16_from_v8s8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: anyext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<8 x i8>) = COPY $d0
    %1:fpr(<8 x i16>) = G_ANYEXT %0(<8 x i8>)
    $q0 = COPY %1(<8 x i16>)
    RET_ReallyLR implicit $q0
...

---
name:            anyext_v4s32_from_v4s16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: anyext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<4 x i16>) = COPY $d0
    %1:fpr(<4 x i32>) = G_ANYEXT %0(<4 x i16>)
    $q0 = COPY %1(<4 x i32>)
    RET_ReallyLR implicit $q0
...

---
name:            anyext_v2s64_from_v2s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: anyext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<2 x i32>) = COPY $d0
    %1:fpr(<2 x i64>) = G_ANYEXT %0(<2 x i32>)
    $q0 = COPY %1(<2 x i64>)
    RET_ReallyLR implicit $q0
...

---
name:            zext_s64_from_s32
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: zext_s64_from_s32
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
    %0(i32) = COPY $w0
    %1(i64) = G_ZEXT %0
    $x0 = COPY %1(i64)
...

---
name:            zext_s32_from_s16
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: zext_s32_from_s16
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
    ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
    %2:gpr(i32) = COPY $w0
    %0(i16) = G_TRUNC %2
    %1(i32) = G_ZEXT %0
    $w0 = COPY %1
...

---
name:            zext_s32_from_s8
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: zext_s32_from_s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
    ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
    %2:gpr(i32) = COPY $w0
    %0(i16) = G_TRUNC %2
    %1(i32) = G_ZEXT %0
    $w0 = COPY %1(i32)
...

---
name:            zext_s16_from_s8
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: zext_s16_from_s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
    %2:gpr(i32) = COPY $w0
    %0(i8) = G_TRUNC %2
    %1(i16) = G_ZEXT %0
    %3:gpr(i32) = G_ANYEXT %1
    $w0 = COPY %3(i32)
...

---
name:            zext_v8s16_from_v8s8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: zext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<8 x i8>) = COPY $d0
    %1:fpr(<8 x i16>) = G_ZEXT %0(<8 x i8>)
    $q0 = COPY %1(<8 x i16>)
    RET_ReallyLR implicit $q0

...

---
name:            zext_v4s32_from_v4s16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: zext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<4 x i16>) = COPY $d0
    %1:fpr(<4 x i32>) = G_ZEXT %0(<4 x i16>)
    $q0 = COPY %1(<4 x i32>)
    RET_ReallyLR implicit $q0
...

---
name:            zext_v2s64_from_v2s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: zext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<2 x i32>) = COPY $d0
    %1:fpr(<2 x i64>) = G_ZEXT %0(<2 x i32>)
    $q0 = COPY %1(<2 x i64>)
    RET_ReallyLR implicit $q0
...

---
name:            sext_s64_from_s32
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: sext_s64_from_s32
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
    ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
    ; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
    %0(i32) = COPY $w0
    %1(i64) = G_SEXT %0
    $x0 = COPY %1(i64)
...

---
name:            sext_s32_from_s16
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: sext_s32_from_s16
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
    ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
    %2:gpr(i32) = COPY $w0
    %0(i16) = G_TRUNC %2
    %1(i32) = G_SEXT %0
    $w0 = COPY %1
...

---
name:            sext_s32_from_s8
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: sext_s32_from_s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
    ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
    %2:gpr(i32) = COPY $w0
    %0(i8) = G_TRUNC %2
    %1(i32) = G_SEXT %0
    $w0 = COPY %1(i32)
...

---
name:            sext_s16_from_s8
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: sext_s16_from_s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
    %2:gpr(i32) = COPY $w0
    %0(i8) = G_TRUNC %2
    %1(i16) = G_SEXT %0
    %3:gpr(i32) = G_ANYEXT %1
    $w0 = COPY %3(i32)
...

---
name:            sext_v8s16_from_v8s8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: sext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[SSHLLv8i8_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<8 x i8>) = COPY $d0
    %1:fpr(<8 x i16>) = G_SEXT %0(<8 x i8>)
    $q0 = COPY %1(<8 x i16>)
    RET_ReallyLR implicit $q0

...

---
name:            sext_v4s32_from_v4s16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: sext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[SSHLLv4i16_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<4 x i16>) = COPY $d0
    %1:fpr(<4 x i32>) = G_SEXT %0(<4 x i16>)
    $q0 = COPY %1(<4 x i32>)
    RET_ReallyLR implicit $q0
...

---
name:            sext_v2s64_from_v2s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: sext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
    ; CHECK-NEXT: $q0 = COPY [[SSHLLv2i32_shift]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<2 x i32>) = COPY $d0
    %1:fpr(<2 x i64>) = G_SEXT %0(<2 x i32>)
    $q0 = COPY %1(<2 x i64>)
    RET_ReallyLR implicit $q0