test/CodeGen/AArch64/GlobalISel/irtranslator-memset-inline.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+mops -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s

define void @memset(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: memset
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64), 0 :: (store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  call void @llvm.memset.p0.i32(ptr %dst, i8 %val, i32 4, i1 false)
  ret void
}

define void @inline_memset(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: inline_memset
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET_INLINE [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64) :: (store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  call void @llvm.memset.inline.p0.i32(ptr %dst, i8 %val, i32 4, i1 false)
  ret void
}

define void @memset_volatile(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: memset_volatile
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64), 0 :: (volatile store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  call void @llvm.memset.p0.i32(ptr %dst, i8 %val, i32 4, i1 true)
  ret void
}

define void @inline_memset_volatile(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: inline_memset_volatile
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET_INLINE [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  call void @llvm.memset.inline.p0.i32(ptr %dst, i8 %val, i32 4, i1 true)
  ret void
}

define void @tail_memset(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: tail_memset
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64), 1 :: (store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void @llvm.memset.p0.i32(ptr %dst, i8 %val, i32 4, i1 false)
  ret void
}

define void @tail_inline_memset(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: tail_inline_memset
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET_INLINE [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64) :: (store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void @llvm.memset.inline.p0.i32(ptr %dst, i8 %val, i32 4, i1 false)
  ret void
}

define void @tail_memset_volatile(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: tail_memset_volatile
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64), 1 :: (volatile store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void @llvm.memset.p0.i32(ptr %dst, i8 %val, i32 4, i1 true)
  ret void
}

define void @tail_inline_memset_volatile(ptr %dst, i8 %val) {
  ; CHECK-LABEL: name: tail_inline_memset_volatile
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w1, $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
  ; CHECK-NEXT:   G_MEMSET_INLINE [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void @llvm.memset.inline.p0.i32(ptr %dst, i8 %val, i32 4, i1 true)
  ret void
}

declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) nounwind
declare void @llvm.memset.inline.p0.i32(ptr nocapture writeonly, i8, i32, i1) nounwind