test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-darwin-ios13 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s

define void @asm_simple_memory_clobber() {
  ; CHECK-LABEL: name: asm_simple_memory_clobber
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, !0
  ; CHECK-NEXT:   INLINEASM &"", sideeffect attdialect, !0
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "", "~{memory}"(), !srcloc !0
  call void asm sideeffect "", ""(), !srcloc !0
  ret void
}

!0 = !{i32 70}

define void @asm_simple_register_clobber() {
  ; CHECK-LABEL: name: asm_simple_register_clobber
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"mov x0, 7", sideeffect attdialect, clobber, implicit-def early-clobber $x0, !0
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "mov x0, 7", "~{x0}"(), !srcloc !0
  ret void
}

define i64 @asm_register_early_clobber() {
  ; CHECK-LABEL: name: asm_register_early_clobber
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"mov $0, 7; mov $1, 7", sideeffect attdialect, regdef-ec:GPR64common, def early-clobber %0, regdef-ec:GPR64common, def early-clobber %1, !0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i64) = COPY %0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i64) = COPY %1
  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(i64) = G_ADD [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   $x0 = COPY [[ADD]](i64)
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0
  %asmresult = extractvalue { i64, i64 } %1, 0
  %asmresult1 = extractvalue { i64, i64 } %1, 1
  %add = add i64 %asmresult, %asmresult1
  ret i64 %add
}

define i32 @test_specific_register_output() nounwind ssp {
  ; CHECK-LABEL: name: test_specific_register_output
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", attdialect, regdef, implicit-def $w0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i32) = COPY $w0
  ; CHECK-NEXT:   $w0 = COPY [[COPY]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  %0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind
  ret i32 %0
}

define i32 @test_single_register_output() nounwind ssp {
  ; CHECK-LABEL: name: test_single_register_output
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", attdialect, regdef:GPR32common, def %0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i32) = COPY %0
  ; CHECK-NEXT:   $w0 = COPY [[COPY]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
  ret i32 %0
}

define i64 @test_single_register_output_s64() nounwind ssp {
  ; CHECK-LABEL: name: test_single_register_output_s64
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   INLINEASM &"mov $0, 7", attdialect, regdef:GPR64common, def %0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i64) = COPY %0
  ; CHECK-NEXT:   $x0 = COPY [[COPY]](i64)
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
entry:
  %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
  ret i64 %0
}

; Check support for returning several floats
define float @test_multiple_register_outputs_same() #0 {
  ; CHECK-LABEL: name: test_multiple_register_outputs_same
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", attdialect, regdef:GPR32common, def %0, regdef:GPR32common, def %1
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(f32) = COPY %0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(f32) = COPY %1
  ; CHECK-NEXT:   [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   $s0 = COPY [[FADD]](f32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
  %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
  %asmresult = extractvalue { float, float } %1, 0
  %asmresult1 = extractvalue { float, float } %1, 1
  %add = fadd float %asmresult, %asmresult1
  ret float %add
}

; Check support for returning several floats
define double @test_multiple_register_outputs_mixed() #0 {
  ; CHECK-LABEL: name: test_multiple_register_outputs_mixed
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", attdialect, regdef:GPR32common, def %0, regdef:FPR64, def %1
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(f32) = COPY %0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(f64) = COPY %1
  ; CHECK-NEXT:   $d0 = COPY [[COPY1]](f64)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  %1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()
  %asmresult = extractvalue { float, double } %1, 1
  ret double %asmresult
}

define i32 @test_specific_register_output_trunc() nounwind ssp {
  ; CHECK-LABEL: name: test_specific_register_output_trunc
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", attdialect, regdef, implicit-def $x0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](s64)
  ; CHECK-NEXT:   $w0 = COPY [[TRUNC]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  %0 = tail call i32 asm "mov ${0:w}, 7", "={x0}"() nounwind
  ret i32 %0
}

define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {
  ; CHECK-LABEL: name: test_register_output_trunc
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 32", attdialect, regdef:GPR32common, def %1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](s32)
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
  ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  %0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind
  ret i8 %0
}

define float @test_vector_output() nounwind {
  ; CHECK-LABEL: name: test_vector_output
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   INLINEASM &"fmov ${0}.2s, #1.0", sideeffect attdialect, regdef, implicit-def $d14
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d14
  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C]](i64)
  ; CHECK-NEXT:   $s0 = COPY [[EVEC]](f32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
  %1 = tail call <2 x float> asm sideeffect "fmov ${0}.2s, #1.0", "={v14}"() nounwind
  %2 = extractelement <2 x float> %1, i32 0
  ret float %2
}

define void @test_input_register_imm() {
  ; CHECK-LABEL: name: test_input_register_imm
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](i64)
  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", sideeffect attdialect, reguse:GPR64common, [[COPY]]
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "mov x0, $0", "r"(i64 42)
  ret void
}

; Make sure that boolean immediates are properly (zero) extended.
define i32 @test_boolean_imm_ext() {
  ; CHECK-LABEL: name: test_boolean_imm_ext
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
  ; CHECK-NEXT:   INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", sideeffect mayload attdialect, imm, 1
  ; CHECK-NEXT:   $w0 = COPY [[C]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true)
  ret i32 1
}

define void @test_input_imm() {
  ; CHECK-LABEL: name: test_input_imm
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", sideeffect mayload attdialect, imm, 42
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "mov x0, $0", "i"(i64 42)
  ret void
}

@var = global i64 0, align 8
define void @test_immediate_constraint_sym() {
  ; CHECK-LABEL: name: test_immediate_constraint_sym
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"#TEST $0", sideeffect mayload attdialect, imm, @var
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "#TEST $0", "i"(ptr @var)
  ret void
}

define void @test_s_constraint() {
  ; CHECK-LABEL: name: test_s_constraint
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   INLINEASM &"#TEST $0", sideeffect mayload attdialect, imm, @var
  ; CHECK-NEXT:   RET_ReallyLR
  call void asm sideeffect "#TEST $0", "s"(ptr @var)
  ret void
}

define zeroext i8 @test_input_register(ptr %src) nounwind {
  ; CHECK-LABEL: name: test_input_register
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
  ; CHECK-NEXT:   INLINEASM &"ldtrb ${0:w}, [$1]", attdialect, regdef:GPR32common, def %1, reguse:GPR64common, [[COPY1]]
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY %1
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](s32)
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
  ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
entry:
  %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind
  ret i8 %0
}

define i32 @test_memory_constraint(ptr %a) nounwind {
  ; CHECK-LABEL: name: test_memory_constraint
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
  ; CHECK-NEXT:   INLINEASM &"ldr $0, $1", mayload attdialect, regdef:GPR32common, def %1, mem:m, [[COPY]](p0)
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY %1
  ; CHECK-NEXT:   $w0 = COPY [[COPY1]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(ptr elementtype(i32) %a)
  ret i32 %1
}

define i16 @test_anyext_input() {
  ; CHECK-LABEL: name: test_anyext_input
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect attdialect, regdef:GPR32common, def %0, reguse:GPR32common, [[COPY]]
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
  ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
  ; CHECK-NEXT:   $w0 = COPY [[ANYEXT1]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  %1 = call i16 asm sideeffect "", "=r,r"(i16 1)
  ret i16 %1
}

define i16 @test_anyext_input_with_matching_constraint() {
  ; CHECK-LABEL: name: test_anyext_input_with_matching_constraint
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect attdialect, regdef:GPR32common, def %0, reguse tiedto:$0, [[COPY]](tied-def 3)
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
  ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
  ; CHECK-NEXT:   $w0 = COPY [[ANYEXT1]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  %1 = call i16 asm sideeffect "", "=r,0"(i16 1)
  ret i16 %1
}

define i64 @test_input_with_matching_constraint_to_physical_register() {
  ; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64arg = COPY [[C]](i64)
  ; CHECK-NEXT:   INLINEASM &"", attdialect, regdef, implicit-def $x2, reguse tiedto:$0, [[COPY]](tied-def 3)
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
  ; CHECK-NEXT:   $x0 = COPY [[COPY1]](i64)
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  %1 = tail call i64 asm "", "={x2},0"(i64 0)
  ret i64 %1
}

define void @test_indirectify_i32_value(i32 %x, i32 %y) {
  ; CHECK-LABEL: name: test_indirectify_i32_value
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i32) = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[COPY]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
  ; CHECK-NEXT:   [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
  ; CHECK-NEXT:   G_STORE [[COPY1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0), mem:m, [[FRAME_INDEX1]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
  ret void
}

define void @test_indirectify_i32_constant() {
  ; CHECK-LABEL: name: test_indirectify_i32_constant
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
  ; CHECK-NEXT:   [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
  ; CHECK-NEXT:   G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0), mem:m, [[FRAME_INDEX1]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)
  ret void
}

define void @test_indirectify_i16_value(i16 %val) {
  ; CHECK-LABEL: name: test_indirectify_i16_value
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i32) = COPY $w0
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[TRUNC]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)
  ret void
}

define void @test_indirectify_i16_constant() {
  ; CHECK-LABEL: name: test_indirectify_i16_constant
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 42
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[C]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,~{memory}"(i16 42)
  ret void
}

define void @test_indirectify_i64_value(i64 %val) {
  ; CHECK-LABEL: name: test_indirectify_i64_value
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i64) = COPY $x0
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[COPY]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)
  ret void
}

define void @test_indirectify_i64_constant() {
  ; CHECK-LABEL: name: test_indirectify_i64_constant
  ; CHECK: bb.1.entry:
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
  ; CHECK-NEXT:   G_STORE [[C]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
  ; CHECK-NEXT:   INLINEASM &"", sideeffect mayload maystore attdialect, mem:m, [[FRAME_INDEX]](p0)
  ; CHECK-NEXT:   RET_ReallyLR
entry:
  tail call void asm sideeffect "", "imr,~{memory}"(i64 42)
  ret void
}

; TODO: add more types