| # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| # RUN: llc -mtriple=riscv64 -mattr=+m,+v -o - %s \ |
| # RUN: -start-before=prologepilog | FileCheck %s |
| # |
| # This test checks that we are assigning the right stack slot to GPRs and to |
| # vector registers (VRs). If this test changes, make sure there is no overlap |
| # between slots for GPRs and VRs. |
| --- | |
| define void @foo() #0 { |
| ; CHECK-LABEL: foo: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: addi sp, sp, -48 |
| ; CHECK-NEXT: sd s9, 40(sp) # 8-byte Folded Spill |
| ; CHECK-NEXT: csrr a1, vlenb |
| ; CHECK-NEXT: slli a1, a1, 1 |
| ; CHECK-NEXT: sub sp, sp, a1 |
| ; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill |
| ; CHECK-NEXT: addi a0, sp, 32 |
| ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill |
| ; CHECK-NEXT: csrr a0, vlenb |
| ; CHECK-NEXT: slli a0, a0, 1 |
| ; CHECK-NEXT: add sp, sp, a0 |
| ; CHECK-NEXT: ld s9, 40(sp) # 8-byte Folded Reload |
| ; CHECK-NEXT: addi sp, sp, 48 |
| ; CHECK-NEXT: ret |
| entry: |
| ret void |
| } |
| |
| attributes #0 = { nounwind } |
| ... |
| --- |
| name: foo |
| alignment: 2 |
| tracksRegLiveness: true |
| frameInfo: |
| maxAlignment: 8 |
| stack: |
| - { id: 0, type: spill-slot, size: 8, alignment: 8 } |
| - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } |
| machineFunctionInfo: {} |
| body: | |
| bb.0.entry: |
| liveins: $x10, $v30m2 |
| |
| $x25 = COPY $x10 |
| SD renamable $x25, %stack.0, 0 :: (store (s64) into %stack.0) |
| VS2R_V renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8) |
| PseudoRET |
| |
| ... |