| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \ |
| ; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s |
| ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \ |
| ; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s |
| ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \ |
| ; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s |
| ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \ |
| ; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s |
| ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation \ |
| ; RUN: | FileCheck -check-prefix=RV32I %s |
| ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ |
| ; RUN: -verify-machineinstrs -disable-strictnode-mutation \ |
| ; RUN: | FileCheck -check-prefix=RV64I %s |
| |
| declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata) |
| |
| define float @sqrt_f32(float %a) nounwind strictfp { |
| ; CHECKIF-LABEL: sqrt_f32: |
| ; CHECKIF: # %bb.0: |
| ; CHECKIF-NEXT: fsqrt.s fa0, fa0 |
| ; CHECKIF-NEXT: ret |
| ; |
| ; CHECKIZFINX-LABEL: sqrt_f32: |
| ; CHECKIZFINX: # %bb.0: |
| ; CHECKIZFINX-NEXT: fsqrt.s a0, a0 |
| ; CHECKIZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: sqrt_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call sqrtf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: sqrt_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call sqrtf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.sqrt.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.powi.f32.i32(float, i32, metadata, metadata) |
| |
| define float @powi_f32(float %a, i32 %b) nounwind strictfp { |
| ; RV32IF-LABEL: powi_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call __powisf2@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: powi_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: sext.w a0, a0 |
| ; RV64IF-NEXT: call __powisf2@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: powi_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call __powisf2@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: powi_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: sext.w a1, a1 |
| ; RV64IZFINX-NEXT: call __powisf2@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: powi_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call __powisf2@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: powi_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: sext.w a1, a1 |
| ; RV64I-NEXT: call __powisf2@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.powi.f32.i32(float %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.sin.f32(float, metadata, metadata) |
| |
| define float @sin_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: sin_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call sinf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: sin_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call sinf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: sin_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call sinf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: sin_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call sinf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: sin_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call sinf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: sin_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call sinf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.cos.f32(float, metadata, metadata) |
| |
| define float @cos_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: cos_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call cosf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: cos_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call cosf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: cos_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call cosf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: cos_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call cosf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: cos_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call cosf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: cos_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call cosf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| ; The sin+cos combination results in an FSINCOS SelectionDAG node. |
| define float @sincos_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: sincos_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: fmv.s fs0, fa0 |
| ; RV32IF-NEXT: call sinf@plt |
| ; RV32IF-NEXT: fmv.s fs1, fa0 |
| ; RV32IF-NEXT: fmv.s fa0, fs0 |
| ; RV32IF-NEXT: call cosf@plt |
| ; RV32IF-NEXT: fadd.s fa0, fs1, fa0 |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: sincos_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill |
| ; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill |
| ; RV64IF-NEXT: fmv.s fs0, fa0 |
| ; RV64IF-NEXT: call sinf@plt |
| ; RV64IF-NEXT: fmv.s fs1, fa0 |
| ; RV64IF-NEXT: fmv.s fa0, fs0 |
| ; RV64IF-NEXT: call cosf@plt |
| ; RV64IF-NEXT: fadd.s fa0, fs1, fa0 |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload |
| ; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: sincos_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: mv s0, a0 |
| ; RV32IZFINX-NEXT: call sinf@plt |
| ; RV32IZFINX-NEXT: mv s1, a0 |
| ; RV32IZFINX-NEXT: mv a0, s0 |
| ; RV32IZFINX-NEXT: call cosf@plt |
| ; RV32IZFINX-NEXT: fadd.s a0, s1, a0 |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: sincos_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -32 |
| ; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: mv s0, a0 |
| ; RV64IZFINX-NEXT: call sinf@plt |
| ; RV64IZFINX-NEXT: mv s1, a0 |
| ; RV64IZFINX-NEXT: mv a0, s0 |
| ; RV64IZFINX-NEXT: call cosf@plt |
| ; RV64IZFINX-NEXT: fadd.s a0, s1, a0 |
| ; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 32 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: sincos_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: mv s0, a0 |
| ; RV32I-NEXT: call sinf@plt |
| ; RV32I-NEXT: mv s1, a0 |
| ; RV32I-NEXT: mv a0, s0 |
| ; RV32I-NEXT: call cosf@plt |
| ; RV32I-NEXT: mv a1, a0 |
| ; RV32I-NEXT: mv a0, s1 |
| ; RV32I-NEXT: call __addsf3@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: sincos_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -32 |
| ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: mv s0, a0 |
| ; RV64I-NEXT: call sinf@plt |
| ; RV64I-NEXT: mv s1, a0 |
| ; RV64I-NEXT: mv a0, s0 |
| ; RV64I-NEXT: call cosf@plt |
| ; RV64I-NEXT: mv a1, a0 |
| ; RV64I-NEXT: mv a0, s1 |
| ; RV64I-NEXT: call __addsf3@plt |
| ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 32 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.sin.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| %2 = call float @llvm.experimental.constrained.cos.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| %3 = fadd float %1, %2 |
| ret float %3 |
| } |
| |
| declare float @llvm.experimental.constrained.pow.f32(float, float, metadata, metadata) |
| |
| define float @pow_f32(float %a, float %b) nounwind strictfp { |
| ; RV32IF-LABEL: pow_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call powf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: pow_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call powf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: pow_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call powf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: pow_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call powf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: pow_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call powf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: pow_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call powf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.pow.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.exp.f32(float, metadata, metadata) |
| |
| define float @exp_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: exp_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call expf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: exp_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call expf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: exp_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call expf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: exp_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call expf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: exp_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call expf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: exp_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call expf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.exp.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.exp2.f32(float, metadata, metadata) |
| |
| define float @exp2_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: exp2_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call exp2f@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: exp2_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call exp2f@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: exp2_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call exp2f@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: exp2_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call exp2f@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: exp2_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call exp2f@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: exp2_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call exp2f@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.exp2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.log.f32(float, metadata, metadata) |
| |
| define float @log_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: log_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call logf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: log_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call logf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: log_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call logf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: log_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call logf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: log_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call logf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: log_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call logf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.log.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.log10.f32(float, metadata, metadata) |
| |
| define float @log10_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: log10_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call log10f@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: log10_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call log10f@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: log10_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call log10f@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: log10_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call log10f@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: log10_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call log10f@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: log10_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call log10f@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.log10.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.log2.f32(float, metadata, metadata) |
| |
| define float @log2_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: log2_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call log2f@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: log2_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call log2f@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: log2_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call log2f@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: log2_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call log2f@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: log2_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call log2f@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: log2_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call log2f@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) |
| |
| define float @fma_f32(float %a, float %b, float %c) nounwind strictfp { |
| ; CHECKIF-LABEL: fma_f32: |
| ; CHECKIF: # %bb.0: |
| ; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2 |
| ; CHECKIF-NEXT: ret |
| ; |
| ; CHECKIZFINX-LABEL: fma_f32: |
| ; CHECKIZFINX: # %bb.0: |
| ; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2 |
| ; CHECKIZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: fma_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call fmaf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: fma_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call fmaf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata) |
| |
| define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp { |
| ; CHECKIF-LABEL: fmuladd_f32: |
| ; CHECKIF: # %bb.0: |
| ; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2 |
| ; CHECKIF-NEXT: ret |
| ; |
| ; CHECKIZFINX-LABEL: fmuladd_f32: |
| ; CHECKIZFINX: # %bb.0: |
| ; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2 |
| ; CHECKIZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: fmuladd_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: mv s0, a2 |
| ; RV32I-NEXT: call __mulsf3@plt |
| ; RV32I-NEXT: mv a1, s0 |
| ; RV32I-NEXT: call __addsf3@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: fmuladd_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: mv s0, a2 |
| ; RV64I-NEXT: call __mulsf3@plt |
| ; RV64I-NEXT: mv a1, s0 |
| ; RV64I-NEXT: call __addsf3@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.fmuladd.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.minnum.f32(float, float, metadata) |
| |
| define float @minnum_f32(float %a, float %b) nounwind strictfp { |
| ; RV32IF-LABEL: minnum_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call fminf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: minnum_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call fminf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: minnum_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call fminf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: minnum_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call fminf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: minnum_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call fminf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: minnum_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call fminf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.minnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) |
| |
| define float @maxnum_f32(float %a, float %b) nounwind strictfp { |
| ; RV32IF-LABEL: maxnum_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call fmaxf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: maxnum_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call fmaxf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: maxnum_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call fmaxf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: maxnum_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call fmaxf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: maxnum_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call fmaxf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: maxnum_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call fmaxf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| ; TODO: FMINNAN and FMAXNAN aren't handled in |
| ; SelectionDAGLegalize::ExpandNode. |
| |
| ; declare float @llvm.experimental.constrained.minimum.f32(float, float, metadata) |
| |
| ; define float @fminimum_f32(float %a, float %b) nounwind strictfp { |
| ; %1 = call float @llvm.experimental.constrained.minimum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp |
| ; ret float %1 |
| ; } |
| |
| ; declare float @llvm.experimental.constrained.maximum.f32(float, float, metadata) |
| |
| ; define float @fmaximum_f32(float %a, float %b) nounwind strictfp { |
| ; %1 = call float @llvm.experimental.constrained.maximum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp |
| ; ret float %1 |
| ; } |
| |
| declare float @llvm.experimental.constrained.floor.f32(float, metadata) |
| |
| define float @floor_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: floor_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call floorf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: floor_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call floorf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: floor_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call floorf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: floor_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call floorf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: floor_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call floorf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: floor_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call floorf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.floor.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.ceil.f32(float, metadata) |
| |
| define float @ceil_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: ceil_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call ceilf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: ceil_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call ceilf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: ceil_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call ceilf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: ceil_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call ceilf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: ceil_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call ceilf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: ceil_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call ceilf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.ceil.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.trunc.f32(float, metadata) |
| |
| define float @trunc_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: trunc_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call truncf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: trunc_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call truncf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: trunc_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call truncf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: trunc_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call truncf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: trunc_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call truncf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: trunc_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call truncf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.trunc.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.rint.f32(float, metadata, metadata) |
| |
| define float @rint_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: rint_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call rintf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: rint_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call rintf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: rint_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call rintf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: rint_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call rintf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: rint_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call rintf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: rint_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call rintf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.rint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.nearbyint.f32(float, metadata, metadata) |
| |
| define float @nearbyint_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: nearbyint_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call nearbyintf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: nearbyint_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call nearbyintf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: nearbyint_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call nearbyintf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: nearbyint_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call nearbyintf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: nearbyint_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call nearbyintf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: nearbyint_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call nearbyintf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.nearbyint.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.round.f32(float, metadata) |
| |
| define float @round_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: round_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call roundf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: round_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call roundf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: round_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call roundf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: round_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call roundf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: round_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call roundf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: round_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call roundf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.round.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare float @llvm.experimental.constrained.roundeven.f32(float, metadata) |
| |
| define float @roundeven_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: roundeven_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call roundevenf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: roundeven_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: addi sp, sp, -16 |
| ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IF-NEXT: call roundevenf@plt |
| ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IF-NEXT: addi sp, sp, 16 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: roundeven_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call roundevenf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: roundeven_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: addi sp, sp, -16 |
| ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64IZFINX-NEXT: call roundevenf@plt |
| ; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64IZFINX-NEXT: addi sp, sp, 16 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: roundeven_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call roundevenf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: roundeven_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call roundevenf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call float @llvm.experimental.constrained.roundeven.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret float %1 |
| } |
| |
| declare iXLen @llvm.experimental.constrained.lrint.iXLen.f32(float, metadata, metadata) |
| |
| define iXLen @lrint_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: lrint_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: fcvt.w.s a0, fa0 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: lrint_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: fcvt.l.s a0, fa0 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: lrint_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: fcvt.w.s a0, a0 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: lrint_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: fcvt.l.s a0, a0 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: lrint_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call lrintf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: lrint_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call lrintf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret iXLen %1 |
| } |
| |
| declare iXLen @llvm.experimental.constrained.lround.iXLen.f32(float, metadata) |
| |
| define iXLen @lround_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: lround_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: lround_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: lround_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: lround_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: fcvt.l.s a0, a0 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: lround_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call lroundf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: lround_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call lroundf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret iXLen %1 |
| } |
| |
| declare i64 @llvm.experimental.constrained.llrint.i64.f32(float, metadata, metadata) |
| |
| define i64 @llrint_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: llrint_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call llrintf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: llrint_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: fcvt.l.s a0, fa0 |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: llrint_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call llrintf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: llrint_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: fcvt.l.s a0, a0 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: llrint_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call llrintf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: llrint_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call llrintf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp |
| ret i64 %1 |
| } |
| |
| declare i64 @llvm.experimental.constrained.llround.i64.f32(float, metadata) |
| |
| define i64 @llround_f32(float %a) nounwind strictfp { |
| ; RV32IF-LABEL: llround_f32: |
| ; RV32IF: # %bb.0: |
| ; RV32IF-NEXT: addi sp, sp, -16 |
| ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IF-NEXT: call llroundf@plt |
| ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IF-NEXT: addi sp, sp, 16 |
| ; RV32IF-NEXT: ret |
| ; |
| ; RV64IF-LABEL: llround_f32: |
| ; RV64IF: # %bb.0: |
| ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm |
| ; RV64IF-NEXT: ret |
| ; |
| ; RV32IZFINX-LABEL: llround_f32: |
| ; RV32IZFINX: # %bb.0: |
| ; RV32IZFINX-NEXT: addi sp, sp, -16 |
| ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32IZFINX-NEXT: call llroundf@plt |
| ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32IZFINX-NEXT: addi sp, sp, 16 |
| ; RV32IZFINX-NEXT: ret |
| ; |
| ; RV64IZFINX-LABEL: llround_f32: |
| ; RV64IZFINX: # %bb.0: |
| ; RV64IZFINX-NEXT: fcvt.l.s a0, a0 |
| ; RV64IZFINX-NEXT: ret |
| ; |
| ; RV32I-LABEL: llround_f32: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -16 |
| ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: call llroundf@plt |
| ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 16 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV64I-LABEL: llround_f32: |
| ; RV64I: # %bb.0: |
| ; RV64I-NEXT: addi sp, sp, -16 |
| ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill |
| ; RV64I-NEXT: call llroundf@plt |
| ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload |
| ; RV64I-NEXT: addi sp, sp, 16 |
| ; RV64I-NEXT: ret |
| %1 = call i64 @llvm.experimental.constrained.llround.i64.f32(float %a, metadata !"fpexcept.strict") strictfp |
| ret i64 %1 |
| } |