| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s |
| --- |
| name: test_subregs_composition_vreg_1024 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_subregs_composition_vreg_1024 |
| ; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1 |
| ; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2 |
| ; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2 |
| ; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3 |
| ; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec |
| ; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3 |
| ; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4 |
| ; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec |
| ; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4 |
| ; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5 |
| ; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec |
| ; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5 |
| ; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7 |
| undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub1_sub2 |
| S_NOP 0, implicit %0.sub2_sub3 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| |
| undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec |
| %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec |
| S_NOP 0, implicit %2.sub1_sub2_sub3_sub4 |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5 |
| |
| undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec |
| %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec |
| S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5 |
| S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6 |
| |
| undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec |
| %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec |
| S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6 |
| S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_64_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_64_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| undef %0.sub0:vreg_64 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| ... |
| --- |
| name: test_vreg_96_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_96_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub2:vreg_96 = V_MOV_B32_e32 22, implicit $exec |
| S_NOP 0, implicit %2.sub2 |
| |
| ... |
| --- |
| name: test_vreg_96_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_96_w64 |
| ; CHECK: undef %2.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_96 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| ... |
| --- |
| name: test_vreg_128_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_128_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec |
| S_NOP 0, implicit %2.sub3 |
| |
| ... |
| --- |
| name: test_vreg_128_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_128_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub2:vreg_128 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3 |
| |
| ... |
| --- |
| name: test_vreg_128_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_128_w96 |
| ; CHECK: undef %2.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_128 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| ... |
| --- |
| name: test_vreg_160_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| S_NOP 0, implicit %2.sub4 |
| |
| ... |
| --- |
| name: test_vreg_160_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4 |
| |
| ... |
| --- |
| name: test_vreg_160_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub2:vreg_160 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4 |
| |
| ... |
| --- |
| name: test_vreg_160_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_w128 |
| ; CHECK: undef %2.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_160 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| ... |
| --- |
| name: test_vreg_192_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub5 |
| |
| ... |
| --- |
| name: test_vreg_192_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5 |
| |
| ... |
| --- |
| name: test_vreg_192_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4_sub5 |
| |
| ... |
| --- |
| name: test_vreg_192_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub2:vreg_192 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5 |
| |
| ... |
| --- |
| name: test_vreg_192_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_w160 |
| ; CHECK: undef %2.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_192 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| ... |
| --- |
| name: test_vreg_224_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub6 |
| |
| ... |
| --- |
| name: test_vreg_224_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub5_sub6 |
| |
| ... |
| --- |
| name: test_vreg_224_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6 |
| |
| ... |
| --- |
| name: test_vreg_224_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4_sub5_sub6 |
| |
| ... |
| --- |
| name: test_vreg_224_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub2:vreg_224 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6 |
| |
| ... |
| --- |
| name: test_vreg_224_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_w192 |
| ; CHECK: undef %2.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %2.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_224 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_224 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| ... |
| --- |
| name: test_vreg_256_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_256 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub2:vreg_256 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_288_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub5_sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub3:vreg_288 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_288_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_w256 |
| ; CHECK: undef %2.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %2.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %2.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %2.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_288 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_288 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_288 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_288 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| --- |
| name: test_vreg_320_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_w256 |
| ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_320 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_320 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_320 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_320 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| undef %2.sub2:vreg_320 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_320 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_352_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub7_sub8_sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_352_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_w256 |
| ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_352 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_352 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_352 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_352 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| undef %2.sub3:vreg_352 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_352 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10 |
| |
| ... |
| --- |
| name: test_vreg_384_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_w256 |
| ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_384 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_384 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_384 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_384 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| undef %2.sub4:vreg_384 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_384 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_512_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec |
| %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub11_sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec |
| %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_w256 |
| ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_512 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_512 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_512 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_512 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| undef %2.sub8:vreg_512 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_512 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec |
| %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_1024_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w32 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]] |
| ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]] |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w64 |
| ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2 |
| |
| undef %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w96 |
| ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3 |
| |
| undef %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w128 |
| ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4 |
| |
| undef %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w160 |
| ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5 |
| |
| undef %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w192 |
| ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 226, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec |
| %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w256 |
| ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 224, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 225, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 226, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8 |
| |
| undef %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec |
| %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec |
| %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec |
| %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_w512 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_w512 |
| ; CHECK: undef %3.sub0:vreg_512 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_512 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_512 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_512 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_512 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_512 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_512 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: %3.sub8:vreg_512 = V_MOV_B32_e32 8, implicit $exec |
| ; CHECK-NEXT: %3.sub9:vreg_512 = V_MOV_B32_e32 9, implicit $exec |
| ; CHECK-NEXT: %3.sub10:vreg_512 = V_MOV_B32_e32 10, implicit $exec |
| ; CHECK-NEXT: %3.sub11:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub12:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub13:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub14:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub15:vreg_512 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_512 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_512 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_512 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_512 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_512 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_512 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_512 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_512 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: %4.sub8:vreg_512 = V_MOV_B32_e32 19, implicit $exec |
| ; CHECK-NEXT: %4.sub9:vreg_512 = V_MOV_B32_e32 110, implicit $exec |
| ; CHECK-NEXT: %4.sub10:vreg_512 = V_MOV_B32_e32 111, implicit $exec |
| ; CHECK-NEXT: %4.sub11:vreg_512 = V_MOV_B32_e32 112, implicit $exec |
| ; CHECK-NEXT: %4.sub12:vreg_512 = V_MOV_B32_e32 113, implicit $exec |
| ; CHECK-NEXT: %4.sub13:vreg_512 = V_MOV_B32_e32 114, implicit $exec |
| ; CHECK-NEXT: %4.sub14:vreg_512 = V_MOV_B32_e32 115, implicit $exec |
| ; CHECK-NEXT: %4.sub15:vreg_512 = V_MOV_B32_e32 116, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_512 = V_MOV_B32_e32 216, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_512 = V_MOV_B32_e32 217, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_512 = V_MOV_B32_e32 218, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_512 = V_MOV_B32_e32 219, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_512 = V_MOV_B32_e32 220, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_512 = V_MOV_B32_e32 221, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_512 = V_MOV_B32_e32 222, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_512 = V_MOV_B32_e32 223, implicit $exec |
| ; CHECK-NEXT: %5.sub8:vreg_512 = V_MOV_B32_e32 224, implicit $exec |
| ; CHECK-NEXT: %5.sub9:vreg_512 = V_MOV_B32_e32 225, implicit $exec |
| ; CHECK-NEXT: %5.sub10:vreg_512 = V_MOV_B32_e32 226, implicit $exec |
| ; CHECK-NEXT: %5.sub11:vreg_512 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub12:vreg_512 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub13:vreg_512 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub14:vreg_512 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub15:vreg_512 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec |
| %0.sub8:vreg_1024 = V_MOV_B32_e32 08, implicit $exec |
| %0.sub9:vreg_1024 = V_MOV_B32_e32 09, implicit $exec |
| %0.sub10:vreg_1024 = V_MOV_B32_e32 010, implicit $exec |
| %0.sub11:vreg_1024 = V_MOV_B32_e32 011, implicit $exec |
| %0.sub12:vreg_1024 = V_MOV_B32_e32 012, implicit $exec |
| %0.sub13:vreg_1024 = V_MOV_B32_e32 013, implicit $exec |
| %0.sub14:vreg_1024 = V_MOV_B32_e32 014, implicit $exec |
| %0.sub15:vreg_1024 = V_MOV_B32_e32 015, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec |
| %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec |
| %1.sub9:vreg_1024 = V_MOV_B32_e32 19, implicit $exec |
| %1.sub10:vreg_1024 = V_MOV_B32_e32 110, implicit $exec |
| %1.sub11:vreg_1024 = V_MOV_B32_e32 111, implicit $exec |
| %1.sub12:vreg_1024 = V_MOV_B32_e32 112, implicit $exec |
| %1.sub13:vreg_1024 = V_MOV_B32_e32 113, implicit $exec |
| %1.sub14:vreg_1024 = V_MOV_B32_e32 114, implicit $exec |
| %1.sub15:vreg_1024 = V_MOV_B32_e32 115, implicit $exec |
| %1.sub16:vreg_1024 = V_MOV_B32_e32 116, implicit $exec |
| S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 |
| |
| undef %2.sub16:vreg_1024 = V_MOV_B32_e32 216, implicit $exec |
| %2.sub17:vreg_1024 = V_MOV_B32_e32 217, implicit $exec |
| %2.sub18:vreg_1024 = V_MOV_B32_e32 218, implicit $exec |
| %2.sub19:vreg_1024 = V_MOV_B32_e32 219, implicit $exec |
| %2.sub20:vreg_1024 = V_MOV_B32_e32 220, implicit $exec |
| %2.sub21:vreg_1024 = V_MOV_B32_e32 221, implicit $exec |
| %2.sub22:vreg_1024 = V_MOV_B32_e32 222, implicit $exec |
| %2.sub23:vreg_1024 = V_MOV_B32_e32 223, implicit $exec |
| %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec |
| %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec |
| %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec |
| %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_subregs_composition_vreg_1024_align2 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_subregs_composition_vreg_1024_align2 |
| ; CHECK: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4.sub0_sub1_sub2 |
| ; CHECK-NEXT: S_NOP 0, implicit %4.sub2_sub3_sub4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1_sub2_sub3 |
| ; CHECK-NEXT: S_NOP 0, implicit %5.sub2_sub3_sub4_sub5 |
| ; CHECK-NEXT: undef %6.sub0:vreg_224_align2 = V_MOV_B32_e32 32, implicit $exec |
| ; CHECK-NEXT: %6.sub2:vreg_224_align2 = V_MOV_B32_e32 34, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2_sub3_sub4 |
| ; CHECK-NEXT: S_NOP 0, implicit %6.sub2_sub3_sub4_sub5_sub6 |
| ; CHECK-NEXT: undef %7.sub0:vreg_256_align2 = V_MOV_B32_e32 42, implicit $exec |
| ; CHECK-NEXT: %7.sub2:vreg_256_align2 = V_MOV_B32_e32 44, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3_sub4_sub5 |
| ; CHECK-NEXT: S_NOP 0, implicit %7.sub2_sub3_sub4_sub5_sub6_sub7 |
| undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| S_NOP 0, implicit %1.sub4_sub5_sub6 |
| |
| undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5 |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7 |
| |
| undef %3.sub2:vreg_1024_align2 = V_MOV_B32_e32 32, implicit $exec |
| %3.sub4:vreg_1024_align2 = V_MOV_B32_e32 34, implicit $exec |
| S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6 |
| S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8 |
| |
| undef %4.sub2:vreg_1024_align2 = V_MOV_B32_e32 42, implicit $exec |
| %4.sub4:vreg_1024_align2 = V_MOV_B32_e32 44, implicit $exec |
| S_NOP 0, implicit %4.sub2_sub3_sub4_sub5_sub6_sub7 |
| S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_64_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_64_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| ... |
| --- |
| name: test_vreg_96_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_96_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub2 |
| undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec |
| S_NOP 0, implicit %2.sub2 |
| |
| ... |
| # Skip test_vreg_96_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_96_align2 |
| --- |
| name: test_vreg_128_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_128_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub3 |
| undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec |
| S_NOP 0, implicit %2.sub3 |
| |
| ... |
| --- |
| name: test_vreg_128_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_128_align2_w64 |
| ; CHECK: undef %2.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_128_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| ... |
| # Skip test_vreg_128_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_128_align2 |
| --- |
| name: test_vreg_160_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub4 |
| undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec |
| S_NOP 0, implicit %2.sub4 |
| |
| ... |
| # Skip test_vreg_160_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_160_align2 |
| --- |
| name: test_vreg_160_align2_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_160_align2_w96 |
| ; CHECK: undef %2.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_160_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_160_align2 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub2:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| |
| ... |
| # Skip test_vreg_160_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_160_align2 |
| --- |
| name: test_vreg_192_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub5 |
| undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub5 |
| |
| ... |
| --- |
| name: test_vreg_192_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub4:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5 |
| |
| ... |
| # Skip test_vreg_192_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_192_align2 |
| --- |
| name: test_vreg_192_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_192_align2_w128 |
| ; CHECK: undef %2.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_192_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_192_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5 |
| |
| ... |
| # Skip test_vreg_192_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_192_align2 |
| --- |
| name: test_vreg_224_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub6 |
| undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub6 |
| |
| ... |
| # Skip test_vreg_224_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_224_align2 |
| --- |
| name: test_vreg_224_align2_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_align2_w96 |
| ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| |
| undef %2.sub4:vreg_224_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_224_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6 |
| |
| ... |
| # Skip test_vreg_224_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_224_align2 |
| --- |
| name: test_vreg_224_align2_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_224_align2_w160 |
| ; CHECK: undef %2.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_224_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_224_align2 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_224_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_224_align2 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6 |
| |
| ... |
| # Skip test_vreg_224_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_224_align2 |
| --- |
| name: test_vreg_256_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub7 |
| undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub7 |
| |
| ... |
| --- |
| name: test_vreg_256_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7 |
| |
| ... |
| # Skip test_vreg_256_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_256_align2 |
| --- |
| name: test_vreg_256_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_align2_w128 |
| ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5 |
| |
| undef %2.sub4:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7 |
| |
| ... |
| # Skip test_vreg_256_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_256_align2 |
| --- |
| name: test_vreg_256_align2_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_256_align2_w192 |
| ; CHECK: undef %2.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %2.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_256_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_256_align2 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_288_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub8 |
| undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub8 |
| |
| ... |
| # Skip test_vreg_288_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_288_align2 |
| --- |
| name: test_vreg_288_align2_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_align2_w96 |
| ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| |
| undef %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8 |
| |
| ... |
| # Skip test_vreg_288_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_288_align2 |
| --- |
| name: test_vreg_288_align2_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_288_align2_w160 |
| ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_288_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_288_align2 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_288_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_288_align2 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub4:vreg_288_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_288_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| # Skip test_vreg_288_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_288_align2 |
| # Skip test_vreg_288_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_288_align2 |
| --- |
| name: test_vreg_320_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub9 |
| undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9 |
| |
| ... |
| # Skip test_vreg_320_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_320_align2 |
| --- |
| name: test_vreg_320_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_align2_w128 |
| ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5 |
| |
| undef %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9 |
| |
| ... |
| # Skip test_vreg_320_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_320_align2 |
| --- |
| name: test_vreg_320_align2_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_align2_w192 |
| ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %2.sub4:vreg_320_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_320_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_320_align2_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_320_align2_w256 |
| ; CHECK: undef %2.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %2.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %2.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %2.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %2.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %2.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %2.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %2.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_320_align2 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_320_align2 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_320_align2 = V_MOV_B32_e32 18, implicit $exec |
| %1.sub9:vreg_320_align2 = V_MOV_B32_e32 19, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| --- |
| name: test_vreg_352_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub10 |
| undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub10 |
| |
| ... |
| # Skip test_vreg_352_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_352_align2 |
| --- |
| name: test_vreg_352_align2_w96 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_align2_w96 |
| ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2 |
| |
| undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4 |
| |
| undef %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10 |
| |
| ... |
| # Skip test_vreg_352_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_352_align2 |
| --- |
| name: test_vreg_352_align2_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_352_align2_w160 |
| ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_352_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_352_align2 = V_MOV_B32_e32 04, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_352_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_352_align2 = V_MOV_B32_e32 16, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6 |
| |
| undef %2.sub6:vreg_352_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_352_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10 |
| |
| ... |
| # Skip test_vreg_352_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_352_align2 |
| # Skip test_vreg_352_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_352_align2 |
| --- |
| name: test_vreg_384_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub11 |
| undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 110, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 111, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub10:vreg_384_align2 = V_MOV_B32_e32 110, implicit $exec |
| %1.sub11:vreg_384_align2 = V_MOV_B32_e32 111, implicit $exec |
| S_NOP 0, implicit %1.sub10_sub11 |
| |
| undef %2.sub2:vreg_384_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_384_align2 = V_MOV_B32_e32 23, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3 |
| |
| ... |
| # Skip test_vreg_384_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_384_align2 |
| --- |
| name: test_vreg_384_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_align2_w128 |
| ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5 |
| |
| undef %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11 |
| |
| ... |
| # Skip test_vreg_384_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_384_align2 |
| --- |
| name: test_vreg_384_align2_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_align2_w192 |
| ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_384_align2_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_384_align2_w256 |
| ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_384_align2 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_384_align2 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_384_align2 = V_MOV_B32_e32 18, implicit $exec |
| %1.sub9:vreg_384_align2 = V_MOV_B32_e32 19, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| undef %2.sub4:vreg_384_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_384_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_vreg_512_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub15 |
| undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub15 |
| |
| ... |
| --- |
| name: test_vreg_512_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 114, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 115, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec |
| %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec |
| S_NOP 0, implicit %1.sub14_sub15 |
| |
| undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3 |
| |
| ... |
| # Skip test_vreg_512_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_512_align2 |
| --- |
| name: test_vreg_512_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_align2_w128 |
| ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 112, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 113, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 114, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 115, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec |
| %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec |
| %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec |
| %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec |
| S_NOP 0, implicit %1.sub12_sub13_sub14_sub15 |
| |
| undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5 |
| |
| ... |
| # Skip test_vreg_512_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_512_align2 |
| --- |
| name: test_vreg_512_align2_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_align2_w192 |
| ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 110, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 111, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 112, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 113, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 114, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 115, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub10:vreg_512_align2 = V_MOV_B32_e32 110, implicit $exec |
| %1.sub11:vreg_512_align2 = V_MOV_B32_e32 111, implicit $exec |
| %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec |
| %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec |
| %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec |
| %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec |
| S_NOP 0, implicit %1.sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| ... |
| --- |
| name: test_vreg_512_align2_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_512_align2_w256 |
| ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_512_align2 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_512_align2 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub2:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_512_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_512_align2 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_512_align2 = V_MOV_B32_e32 18, implicit $exec |
| %1.sub9:vreg_512_align2 = V_MOV_B32_e32 19, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| undef %2.sub8:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec |
| %2.sub12:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_vreg_1024_align2_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w32 |
| ; CHECK: undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %0.sub0 |
| ; CHECK-NEXT: undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub1 |
| ; CHECK-NEXT: undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub31 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_align2_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w64 |
| ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub30_sub31 |
| |
| ... |
| # Skip test_vreg_1024_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_1024_align2 |
| --- |
| name: test_vreg_1024_align2_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w128 |
| ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5 |
| |
| undef %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub28_sub29_sub30_sub31 |
| |
| ... |
| # Skip test_vreg_1024_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_1024_align2 |
| --- |
| name: test_vreg_1024_align2_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w192 |
| ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 226, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec |
| %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_align2_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w256 |
| ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 224, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 225, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 226, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 227, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 228, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 229, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 230, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 231, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec |
| %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec |
| %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec |
| %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec |
| %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec |
| %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec |
| %1.sub8:vreg_1024_align2 = V_MOV_B32_e32 18, implicit $exec |
| %1.sub9:vreg_1024_align2 = V_MOV_B32_e32 19, implicit $exec |
| S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| undef %2.sub24:vreg_1024_align2 = V_MOV_B32_e32 224, implicit $exec |
| %2.sub25:vreg_1024_align2 = V_MOV_B32_e32 225, implicit $exec |
| %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec |
| %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec |
| %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec |
| %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec |
| %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec |
| %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec |
| S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| ... |
| --- |
| name: test_vreg_1024_align2_w512 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_vreg_1024_align2_w512 |
| ; CHECK: undef %3.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: %3.sub1:vreg_512_align2 = V_MOV_B32_e32 1, implicit $exec |
| ; CHECK-NEXT: %3.sub2:vreg_512_align2 = V_MOV_B32_e32 2, implicit $exec |
| ; CHECK-NEXT: %3.sub3:vreg_512_align2 = V_MOV_B32_e32 3, implicit $exec |
| ; CHECK-NEXT: %3.sub4:vreg_512_align2 = V_MOV_B32_e32 4, implicit $exec |
| ; CHECK-NEXT: %3.sub5:vreg_512_align2 = V_MOV_B32_e32 5, implicit $exec |
| ; CHECK-NEXT: %3.sub6:vreg_512_align2 = V_MOV_B32_e32 6, implicit $exec |
| ; CHECK-NEXT: %3.sub7:vreg_512_align2 = V_MOV_B32_e32 7, implicit $exec |
| ; CHECK-NEXT: %3.sub8:vreg_512_align2 = V_MOV_B32_e32 8, implicit $exec |
| ; CHECK-NEXT: %3.sub9:vreg_512_align2 = V_MOV_B32_e32 9, implicit $exec |
| ; CHECK-NEXT: %3.sub10:vreg_512_align2 = V_MOV_B32_e32 10, implicit $exec |
| ; CHECK-NEXT: %3.sub11:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec |
| ; CHECK-NEXT: %3.sub12:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec |
| ; CHECK-NEXT: %3.sub13:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec |
| ; CHECK-NEXT: %3.sub14:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec |
| ; CHECK-NEXT: %3.sub15:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:vreg_512_align2 = V_MOV_B32_e32 116, implicit $exec |
| ; CHECK-NEXT: %4.sub1:vreg_512_align2 = V_MOV_B32_e32 117, implicit $exec |
| ; CHECK-NEXT: %4.sub2:vreg_512_align2 = V_MOV_B32_e32 118, implicit $exec |
| ; CHECK-NEXT: %4.sub3:vreg_512_align2 = V_MOV_B32_e32 119, implicit $exec |
| ; CHECK-NEXT: %4.sub4:vreg_512_align2 = V_MOV_B32_e32 120, implicit $exec |
| ; CHECK-NEXT: %4.sub5:vreg_512_align2 = V_MOV_B32_e32 121, implicit $exec |
| ; CHECK-NEXT: %4.sub6:vreg_512_align2 = V_MOV_B32_e32 122, implicit $exec |
| ; CHECK-NEXT: %4.sub7:vreg_512_align2 = V_MOV_B32_e32 123, implicit $exec |
| ; CHECK-NEXT: %4.sub8:vreg_512_align2 = V_MOV_B32_e32 124, implicit $exec |
| ; CHECK-NEXT: %4.sub9:vreg_512_align2 = V_MOV_B32_e32 125, implicit $exec |
| ; CHECK-NEXT: %4.sub10:vreg_512_align2 = V_MOV_B32_e32 126, implicit $exec |
| ; CHECK-NEXT: %4.sub11:vreg_512_align2 = V_MOV_B32_e32 127, implicit $exec |
| ; CHECK-NEXT: %4.sub12:vreg_512_align2 = V_MOV_B32_e32 128, implicit $exec |
| ; CHECK-NEXT: %4.sub13:vreg_512_align2 = V_MOV_B32_e32 129, implicit $exec |
| ; CHECK-NEXT: %4.sub14:vreg_512_align2 = V_MOV_B32_e32 130, implicit $exec |
| ; CHECK-NEXT: %4.sub15:vreg_512_align2 = V_MOV_B32_e32 131, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec |
| ; CHECK-NEXT: %5.sub2:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec |
| ; CHECK-NEXT: %5.sub3:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec |
| ; CHECK-NEXT: %5.sub4:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec |
| ; CHECK-NEXT: %5.sub5:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec |
| ; CHECK-NEXT: %5.sub6:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec |
| ; CHECK-NEXT: %5.sub7:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec |
| ; CHECK-NEXT: %5.sub8:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec |
| ; CHECK-NEXT: %5.sub9:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec |
| ; CHECK-NEXT: %5.sub10:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec |
| ; CHECK-NEXT: %5.sub11:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec |
| ; CHECK-NEXT: %5.sub12:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec |
| ; CHECK-NEXT: %5.sub13:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec |
| ; CHECK-NEXT: %5.sub14:vreg_512_align2 = V_MOV_B32_e32 216, implicit $exec |
| ; CHECK-NEXT: %5.sub15:vreg_512_align2 = V_MOV_B32_e32 217, implicit $exec |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec |
| %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec |
| %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec |
| %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec |
| %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec |
| %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec |
| %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec |
| %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec |
| %0.sub8:vreg_1024_align2 = V_MOV_B32_e32 08, implicit $exec |
| %0.sub9:vreg_1024_align2 = V_MOV_B32_e32 09, implicit $exec |
| %0.sub10:vreg_1024_align2 = V_MOV_B32_e32 010, implicit $exec |
| %0.sub11:vreg_1024_align2 = V_MOV_B32_e32 011, implicit $exec |
| %0.sub12:vreg_1024_align2 = V_MOV_B32_e32 012, implicit $exec |
| %0.sub13:vreg_1024_align2 = V_MOV_B32_e32 013, implicit $exec |
| %0.sub14:vreg_1024_align2 = V_MOV_B32_e32 014, implicit $exec |
| %0.sub15:vreg_1024_align2 = V_MOV_B32_e32 015, implicit $exec |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| undef %1.sub16:vreg_1024_align2 = V_MOV_B32_e32 116, implicit $exec |
| %1.sub17:vreg_1024_align2 = V_MOV_B32_e32 117, implicit $exec |
| %1.sub18:vreg_1024_align2 = V_MOV_B32_e32 118, implicit $exec |
| %1.sub19:vreg_1024_align2 = V_MOV_B32_e32 119, implicit $exec |
| %1.sub20:vreg_1024_align2 = V_MOV_B32_e32 120, implicit $exec |
| %1.sub21:vreg_1024_align2 = V_MOV_B32_e32 121, implicit $exec |
| %1.sub22:vreg_1024_align2 = V_MOV_B32_e32 122, implicit $exec |
| %1.sub23:vreg_1024_align2 = V_MOV_B32_e32 123, implicit $exec |
| %1.sub24:vreg_1024_align2 = V_MOV_B32_e32 124, implicit $exec |
| %1.sub25:vreg_1024_align2 = V_MOV_B32_e32 125, implicit $exec |
| %1.sub26:vreg_1024_align2 = V_MOV_B32_e32 126, implicit $exec |
| %1.sub27:vreg_1024_align2 = V_MOV_B32_e32 127, implicit $exec |
| %1.sub28:vreg_1024_align2 = V_MOV_B32_e32 128, implicit $exec |
| %1.sub29:vreg_1024_align2 = V_MOV_B32_e32 129, implicit $exec |
| %1.sub30:vreg_1024_align2 = V_MOV_B32_e32 130, implicit $exec |
| %1.sub31:vreg_1024_align2 = V_MOV_B32_e32 131, implicit $exec |
| S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec |
| %2.sub3:vreg_1024_align2 = V_MOV_B32_e32 23, implicit $exec |
| %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec |
| %2.sub5:vreg_1024_align2 = V_MOV_B32_e32 25, implicit $exec |
| %2.sub6:vreg_1024_align2 = V_MOV_B32_e32 26, implicit $exec |
| %2.sub7:vreg_1024_align2 = V_MOV_B32_e32 27, implicit $exec |
| %2.sub8:vreg_1024_align2 = V_MOV_B32_e32 28, implicit $exec |
| %2.sub9:vreg_1024_align2 = V_MOV_B32_e32 29, implicit $exec |
| %2.sub10:vreg_1024_align2 = V_MOV_B32_e32 210, implicit $exec |
| %2.sub11:vreg_1024_align2 = V_MOV_B32_e32 211, implicit $exec |
| %2.sub12:vreg_1024_align2 = V_MOV_B32_e32 212, implicit $exec |
| %2.sub13:vreg_1024_align2 = V_MOV_B32_e32 213, implicit $exec |
| %2.sub14:vreg_1024_align2 = V_MOV_B32_e32 214, implicit $exec |
| %2.sub15:vreg_1024_align2 = V_MOV_B32_e32 215, implicit $exec |
| %2.sub16:vreg_1024_align2 = V_MOV_B32_e32 216, implicit $exec |
| %2.sub17:vreg_1024_align2 = V_MOV_B32_e32 217, implicit $exec |
| S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17 |
| |
| ... |
| --- |
| name: test_subregs_composition_sgpr_1024 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_subregs_composition_sgpr_1024 |
| ; CHECK: undef %2.sub0:sgpr_288 = S_MOV_B32 34 |
| ; CHECK-NEXT: %2.sub4:sgpr_288 = S_MOV_B32 38 |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub0_sub1_sub2_sub3_sub4 |
| ; CHECK-NEXT: S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_320 = S_MOV_B32 44 |
| ; CHECK-NEXT: %3.sub4:sgpr_320 = S_MOV_B32 48 |
| ; CHECK-NEXT: S_NOP 0, implicit %3.sub0_sub1_sub2_sub3_sub4_sub5 |
| ; CHECK-NEXT: S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8_sub9 |
| undef %3.sub4:sgpr_1024 = S_MOV_B32 34 |
| %3.sub8:sgpr_1024 = S_MOV_B32 38 |
| S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8 |
| S_NOP 0, implicit %3.sub8_sub9_sub10_sub11_sub12 |
| |
| undef %4.sub4:sgpr_1024 = S_MOV_B32 44 |
| %4.sub8:sgpr_1024 = S_MOV_B32 48 |
| S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub9 |
| S_NOP 0, implicit %4.sub8_sub9_sub10_sub11_sub12_sub13 |
| |
| ... |
| --- |
| name: test_sgpr_64_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_64_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| undef %0.sub0:sgpr_64 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_64 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| ... |
| --- |
| name: test_sgpr_96_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_96_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 22 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_96 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_96 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub2:sgpr_96 = S_MOV_B32 22 |
| S_NOP 0, implicit %2.sub2 |
| |
| ... |
| # Skip test_sgpr_96_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_96 |
| --- |
| name: test_sgpr_128_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_128_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 23 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_128 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_128 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub3:sgpr_128 = S_MOV_B32 23 |
| S_NOP 0, implicit %2.sub3 |
| |
| ... |
| --- |
| name: test_sgpr_128_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_128_w64 |
| ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_64 = S_MOV_B32 12 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 13 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:sgpr_128 = S_MOV_B32 00 |
| %0.sub1:sgpr_128 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:sgpr_128 = S_MOV_B32 12 |
| %1.sub3:sgpr_128 = S_MOV_B32 13 |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| ... |
| # Skip test_sgpr_128_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_128 |
| --- |
| name: test_sgpr_160_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_160_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 24 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_160 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_160 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub4:sgpr_160 = S_MOV_B32 24 |
| S_NOP 0, implicit %2.sub4 |
| |
| ... |
| # Skip test_sgpr_160_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_160 |
| # Skip test_sgpr_160_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_160 |
| # Skip test_sgpr_160_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_160 |
| --- |
| name: test_sgpr_192_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_192_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 25 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_192 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_192 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub5:sgpr_192 = S_MOV_B32 25 |
| S_NOP 0, implicit %2.sub5 |
| |
| ... |
| --- |
| name: test_sgpr_192_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_192_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 24 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 25 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_192 = S_MOV_B32 00 |
| %0.sub1:sgpr_192 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:sgpr_192 = S_MOV_B32 12 |
| %1.sub3:sgpr_192 = S_MOV_B32 13 |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub4:sgpr_192 = S_MOV_B32 24 |
| %2.sub5:sgpr_192 = S_MOV_B32 25 |
| S_NOP 0, implicit %2.sub4_sub5 |
| |
| ... |
| # Skip test_sgpr_192_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_192 |
| # Skip test_sgpr_192_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_192 |
| # Skip test_sgpr_192_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_192 |
| --- |
| name: test_sgpr_224_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_224_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 26 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_224 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_224 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub6:sgpr_224 = S_MOV_B32 26 |
| S_NOP 0, implicit %2.sub6 |
| |
| ... |
| # Skip test_sgpr_224_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_224 |
| # Skip test_sgpr_224_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_224 |
| # Skip test_sgpr_224_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_224 |
| # Skip test_sgpr_224_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_224 |
| # Skip test_sgpr_224_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_224 |
| --- |
| name: test_sgpr_256_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_256_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 27 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_256 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_256 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub7:sgpr_256 = S_MOV_B32 27 |
| S_NOP 0, implicit %2.sub7 |
| |
| ... |
| --- |
| name: test_sgpr_256_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_256_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 26 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 27 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_256 = S_MOV_B32 00 |
| %0.sub1:sgpr_256 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:sgpr_256 = S_MOV_B32 12 |
| %1.sub3:sgpr_256 = S_MOV_B32 13 |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub6:sgpr_256 = S_MOV_B32 26 |
| %2.sub7:sgpr_256 = S_MOV_B32 27 |
| S_NOP 0, implicit %2.sub6_sub7 |
| |
| ... |
| # Skip test_sgpr_256_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_256 |
| --- |
| name: test_sgpr_256_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_256_w128 |
| ; CHECK: undef %2.sub0:sgpr_128 = S_MOV_B32 0 |
| ; CHECK-NEXT: %2.sub1:sgpr_128 = S_MOV_B32 1 |
| ; CHECK-NEXT: %2.sub2:sgpr_128 = S_MOV_B32 2 |
| ; CHECK-NEXT: %2.sub3:sgpr_128 = S_MOV_B32 3 |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_128 = S_MOV_B32 14 |
| ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 15 |
| ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 16 |
| ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 17 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:sgpr_256 = S_MOV_B32 00 |
| %0.sub1:sgpr_256 = S_MOV_B32 01 |
| %0.sub2:sgpr_256 = S_MOV_B32 02 |
| %0.sub3:sgpr_256 = S_MOV_B32 03 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub4:sgpr_256 = S_MOV_B32 14 |
| %1.sub5:sgpr_256 = S_MOV_B32 15 |
| %1.sub6:sgpr_256 = S_MOV_B32 16 |
| %1.sub7:sgpr_256 = S_MOV_B32 17 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7 |
| |
| ... |
| # Skip test_sgpr_256_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_256 |
| # Skip test_sgpr_256_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_256 |
| --- |
| name: test_sgpr_288_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_288_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 28 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_288 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_288 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub8:sgpr_288 = S_MOV_B32 28 |
| S_NOP 0, implicit %2.sub8 |
| |
| ... |
| # Skip test_sgpr_288_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_288 |
| # Skip test_sgpr_288_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_288 |
| # Skip test_sgpr_288_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_288 |
| --- |
| name: test_sgpr_288_w160 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_288_w160 |
| ; CHECK: undef %2.sub0:sgpr_160 = S_MOV_B32 0 |
| ; CHECK-NEXT: %2.sub1:sgpr_160 = S_MOV_B32 1 |
| ; CHECK-NEXT: %2.sub2:sgpr_160 = S_MOV_B32 2 |
| ; CHECK-NEXT: %2.sub3:sgpr_160 = S_MOV_B32 3 |
| ; CHECK-NEXT: %2.sub4:sgpr_160 = S_MOV_B32 4 |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_160 = S_MOV_B32 14 |
| ; CHECK-NEXT: %3.sub1:sgpr_160 = S_MOV_B32 15 |
| ; CHECK-NEXT: %3.sub2:sgpr_160 = S_MOV_B32 16 |
| ; CHECK-NEXT: %3.sub3:sgpr_160 = S_MOV_B32 17 |
| ; CHECK-NEXT: %3.sub4:sgpr_160 = S_MOV_B32 18 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:sgpr_288 = S_MOV_B32 00 |
| %0.sub1:sgpr_288 = S_MOV_B32 01 |
| %0.sub2:sgpr_288 = S_MOV_B32 02 |
| %0.sub3:sgpr_288 = S_MOV_B32 03 |
| %0.sub4:sgpr_288 = S_MOV_B32 04 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4 |
| |
| undef %1.sub4:sgpr_288 = S_MOV_B32 14 |
| %1.sub5:sgpr_288 = S_MOV_B32 15 |
| %1.sub6:sgpr_288 = S_MOV_B32 16 |
| %1.sub7:sgpr_288 = S_MOV_B32 17 |
| %1.sub8:sgpr_288 = S_MOV_B32 18 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8 |
| |
| ... |
| # Skip test_sgpr_288_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_288 |
| # Skip test_sgpr_288_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_288 |
| --- |
| name: test_sgpr_320_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_320_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 29 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_320 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_320 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub9:sgpr_320 = S_MOV_B32 29 |
| S_NOP 0, implicit %2.sub9 |
| |
| ... |
| --- |
| name: test_sgpr_320_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_320_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 28 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 29 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_320 = S_MOV_B32 00 |
| %0.sub1:sgpr_320 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:sgpr_320 = S_MOV_B32 12 |
| %1.sub3:sgpr_320 = S_MOV_B32 13 |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub8:sgpr_320 = S_MOV_B32 28 |
| %2.sub9:sgpr_320 = S_MOV_B32 29 |
| S_NOP 0, implicit %2.sub8_sub9 |
| |
| ... |
| # Skip test_sgpr_320_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_320 |
| # Skip test_sgpr_320_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_320 |
| # Skip test_sgpr_320_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_320 |
| --- |
| name: test_sgpr_320_w192 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_320_w192 |
| ; CHECK: undef %2.sub0:sgpr_192 = S_MOV_B32 0 |
| ; CHECK-NEXT: %2.sub1:sgpr_192 = S_MOV_B32 1 |
| ; CHECK-NEXT: %2.sub2:sgpr_192 = S_MOV_B32 2 |
| ; CHECK-NEXT: %2.sub3:sgpr_192 = S_MOV_B32 3 |
| ; CHECK-NEXT: %2.sub4:sgpr_192 = S_MOV_B32 4 |
| ; CHECK-NEXT: %2.sub5:sgpr_192 = S_MOV_B32 5 |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_192 = S_MOV_B32 14 |
| ; CHECK-NEXT: %3.sub1:sgpr_192 = S_MOV_B32 15 |
| ; CHECK-NEXT: %3.sub2:sgpr_192 = S_MOV_B32 16 |
| ; CHECK-NEXT: %3.sub3:sgpr_192 = S_MOV_B32 17 |
| ; CHECK-NEXT: %3.sub4:sgpr_192 = S_MOV_B32 18 |
| ; CHECK-NEXT: %3.sub5:sgpr_192 = S_MOV_B32 19 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:sgpr_320 = S_MOV_B32 00 |
| %0.sub1:sgpr_320 = S_MOV_B32 01 |
| %0.sub2:sgpr_320 = S_MOV_B32 02 |
| %0.sub3:sgpr_320 = S_MOV_B32 03 |
| %0.sub4:sgpr_320 = S_MOV_B32 04 |
| %0.sub5:sgpr_320 = S_MOV_B32 05 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5 |
| |
| undef %1.sub4:sgpr_320 = S_MOV_B32 14 |
| %1.sub5:sgpr_320 = S_MOV_B32 15 |
| %1.sub6:sgpr_320 = S_MOV_B32 16 |
| %1.sub7:sgpr_320 = S_MOV_B32 17 |
| %1.sub8:sgpr_320 = S_MOV_B32 18 |
| %1.sub9:sgpr_320 = S_MOV_B32 19 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9 |
| |
| ... |
| # Skip test_sgpr_320_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_320 |
| --- |
| name: test_sgpr_352_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_352_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 210 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_352 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_352 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub10:sgpr_352 = S_MOV_B32 210 |
| S_NOP 0, implicit %2.sub10 |
| |
| ... |
| # Skip test_sgpr_352_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_352 |
| # Skip test_sgpr_352_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_352 |
| # Skip test_sgpr_352_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_352 |
| # Skip test_sgpr_352_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_352 |
| # Skip test_sgpr_352_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_352 |
| # Skip test_sgpr_352_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_352 |
| --- |
| name: test_sgpr_384_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_384_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 211 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_384 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_384 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub11:sgpr_384 = S_MOV_B32 211 |
| S_NOP 0, implicit %2.sub11 |
| |
| ... |
| --- |
| name: test_sgpr_384_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_384_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 110 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 111 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_384 = S_MOV_B32 00 |
| %0.sub1:sgpr_384 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub10:sgpr_384 = S_MOV_B32 110 |
| %1.sub11:sgpr_384 = S_MOV_B32 111 |
| S_NOP 0, implicit %1.sub10_sub11 |
| |
| undef %2.sub2:sgpr_384 = S_MOV_B32 22 |
| %2.sub3:sgpr_384 = S_MOV_B32 23 |
| S_NOP 0, implicit %2.sub2_sub3 |
| |
| ... |
| # Skip test_sgpr_384_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_384 |
| --- |
| name: test_sgpr_384_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_384_w128 |
| ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 14 |
| ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 15 |
| ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 16 |
| ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 17 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 28 |
| ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 29 |
| ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 210 |
| ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 211 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_384 = S_MOV_B32 00 |
| %0.sub1:sgpr_384 = S_MOV_B32 01 |
| %0.sub2:sgpr_384 = S_MOV_B32 02 |
| %0.sub3:sgpr_384 = S_MOV_B32 03 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub4:sgpr_384 = S_MOV_B32 14 |
| %1.sub5:sgpr_384 = S_MOV_B32 15 |
| %1.sub6:sgpr_384 = S_MOV_B32 16 |
| %1.sub7:sgpr_384 = S_MOV_B32 17 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7 |
| |
| undef %2.sub8:sgpr_384 = S_MOV_B32 28 |
| %2.sub9:sgpr_384 = S_MOV_B32 29 |
| %2.sub10:sgpr_384 = S_MOV_B32 210 |
| %2.sub11:sgpr_384 = S_MOV_B32 211 |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11 |
| |
| ... |
| # Skip test_sgpr_384_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_384 |
| # Skip test_sgpr_384_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_384 |
| --- |
| name: test_sgpr_384_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_384_w256 |
| ; CHECK: undef %2.sub0:sgpr_256 = S_MOV_B32 0 |
| ; CHECK-NEXT: %2.sub1:sgpr_256 = S_MOV_B32 1 |
| ; CHECK-NEXT: %2.sub2:sgpr_256 = S_MOV_B32 2 |
| ; CHECK-NEXT: %2.sub3:sgpr_256 = S_MOV_B32 3 |
| ; CHECK-NEXT: %2.sub4:sgpr_256 = S_MOV_B32 4 |
| ; CHECK-NEXT: %2.sub5:sgpr_256 = S_MOV_B32 5 |
| ; CHECK-NEXT: %2.sub6:sgpr_256 = S_MOV_B32 6 |
| ; CHECK-NEXT: %2.sub7:sgpr_256 = S_MOV_B32 7 |
| ; CHECK-NEXT: S_NOP 0, implicit %2 |
| ; CHECK-NEXT: undef %3.sub0:sgpr_256 = S_MOV_B32 14 |
| ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 15 |
| ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 16 |
| ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 17 |
| ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 18 |
| ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 19 |
| ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 110 |
| ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 111 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| undef %0.sub0:sgpr_384 = S_MOV_B32 00 |
| %0.sub1:sgpr_384 = S_MOV_B32 01 |
| %0.sub2:sgpr_384 = S_MOV_B32 02 |
| %0.sub3:sgpr_384 = S_MOV_B32 03 |
| %0.sub4:sgpr_384 = S_MOV_B32 04 |
| %0.sub5:sgpr_384 = S_MOV_B32 05 |
| %0.sub6:sgpr_384 = S_MOV_B32 06 |
| %0.sub7:sgpr_384 = S_MOV_B32 07 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub4:sgpr_384 = S_MOV_B32 14 |
| %1.sub5:sgpr_384 = S_MOV_B32 15 |
| %1.sub6:sgpr_384 = S_MOV_B32 16 |
| %1.sub7:sgpr_384 = S_MOV_B32 17 |
| %1.sub8:sgpr_384 = S_MOV_B32 18 |
| %1.sub9:sgpr_384 = S_MOV_B32 19 |
| %1.sub10:sgpr_384 = S_MOV_B32 110 |
| %1.sub11:sgpr_384 = S_MOV_B32 111 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_sgpr_512_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_512_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 215 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_512 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_512 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub15:sgpr_512 = S_MOV_B32 215 |
| S_NOP 0, implicit %2.sub15 |
| |
| ... |
| --- |
| name: test_sgpr_512_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_512_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 114 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 115 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_512 = S_MOV_B32 00 |
| %0.sub1:sgpr_512 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub14:sgpr_512 = S_MOV_B32 114 |
| %1.sub15:sgpr_512 = S_MOV_B32 115 |
| S_NOP 0, implicit %1.sub14_sub15 |
| |
| undef %2.sub2:sgpr_512 = S_MOV_B32 22 |
| %2.sub3:sgpr_512 = S_MOV_B32 23 |
| S_NOP 0, implicit %2.sub2_sub3 |
| |
| ... |
| # Skip test_sgpr_512_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_512 |
| --- |
| name: test_sgpr_512_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_512_w128 |
| ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 112 |
| ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 113 |
| ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 114 |
| ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 115 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24 |
| ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25 |
| ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26 |
| ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_512 = S_MOV_B32 00 |
| %0.sub1:sgpr_512 = S_MOV_B32 01 |
| %0.sub2:sgpr_512 = S_MOV_B32 02 |
| %0.sub3:sgpr_512 = S_MOV_B32 03 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub12:sgpr_512 = S_MOV_B32 112 |
| %1.sub13:sgpr_512 = S_MOV_B32 113 |
| %1.sub14:sgpr_512 = S_MOV_B32 114 |
| %1.sub15:sgpr_512 = S_MOV_B32 115 |
| S_NOP 0, implicit %1.sub12_sub13_sub14_sub15 |
| |
| undef %2.sub4:sgpr_512 = S_MOV_B32 24 |
| %2.sub5:sgpr_512 = S_MOV_B32 25 |
| %2.sub6:sgpr_512 = S_MOV_B32 26 |
| %2.sub7:sgpr_512 = S_MOV_B32 27 |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7 |
| |
| ... |
| # Skip test_sgpr_512_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_512 |
| # Skip test_sgpr_512_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_512 |
| --- |
| name: test_sgpr_512_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_512_w256 |
| ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3 |
| ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4 |
| ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5 |
| ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6 |
| ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 14 |
| ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 15 |
| ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 16 |
| ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 17 |
| ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 18 |
| ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 19 |
| ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 110 |
| ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 111 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 28 |
| ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 29 |
| ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 210 |
| ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 211 |
| ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 212 |
| ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 213 |
| ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 214 |
| ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 215 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_512 = S_MOV_B32 00 |
| %0.sub1:sgpr_512 = S_MOV_B32 01 |
| %0.sub2:sgpr_512 = S_MOV_B32 02 |
| %0.sub3:sgpr_512 = S_MOV_B32 03 |
| %0.sub4:sgpr_512 = S_MOV_B32 04 |
| %0.sub5:sgpr_512 = S_MOV_B32 05 |
| %0.sub6:sgpr_512 = S_MOV_B32 06 |
| %0.sub7:sgpr_512 = S_MOV_B32 07 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub4:sgpr_512 = S_MOV_B32 14 |
| %1.sub5:sgpr_512 = S_MOV_B32 15 |
| %1.sub6:sgpr_512 = S_MOV_B32 16 |
| %1.sub7:sgpr_512 = S_MOV_B32 17 |
| %1.sub8:sgpr_512 = S_MOV_B32 18 |
| %1.sub9:sgpr_512 = S_MOV_B32 19 |
| %1.sub10:sgpr_512 = S_MOV_B32 110 |
| %1.sub11:sgpr_512 = S_MOV_B32 111 |
| S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| undef %2.sub8:sgpr_512 = S_MOV_B32 28 |
| %2.sub9:sgpr_512 = S_MOV_B32 29 |
| %2.sub10:sgpr_512 = S_MOV_B32 210 |
| %2.sub11:sgpr_512 = S_MOV_B32 211 |
| %2.sub12:sgpr_512 = S_MOV_B32 212 |
| %2.sub13:sgpr_512 = S_MOV_B32 213 |
| %2.sub14:sgpr_512 = S_MOV_B32 214 |
| %2.sub15:sgpr_512 = S_MOV_B32 215 |
| S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| ... |
| --- |
| name: test_sgpr_1024_w32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_1024_w32 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] |
| ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] |
| ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 231 |
| ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]] |
| undef %0.sub0:sgpr_1024 = S_MOV_B32 00 |
| S_NOP 0, implicit %0.sub0 |
| |
| undef %1.sub1:sgpr_1024 = S_MOV_B32 11 |
| S_NOP 0, implicit %1.sub1 |
| |
| undef %2.sub31:sgpr_1024 = S_MOV_B32 231 |
| S_NOP 0, implicit %2.sub31 |
| |
| ... |
| --- |
| name: test_sgpr_1024_w64 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_1024_w64 |
| ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12 |
| ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 230 |
| ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 231 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_1024 = S_MOV_B32 00 |
| %0.sub1:sgpr_1024 = S_MOV_B32 01 |
| S_NOP 0, implicit %0.sub0_sub1 |
| |
| undef %1.sub2:sgpr_1024 = S_MOV_B32 12 |
| %1.sub3:sgpr_1024 = S_MOV_B32 13 |
| S_NOP 0, implicit %1.sub2_sub3 |
| |
| undef %2.sub30:sgpr_1024 = S_MOV_B32 230 |
| %2.sub31:sgpr_1024 = S_MOV_B32 231 |
| S_NOP 0, implicit %2.sub30_sub31 |
| |
| ... |
| # Skip test_sgpr_1024_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_1024 |
| --- |
| name: test_sgpr_1024_w128 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_1024_w128 |
| ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 128 |
| ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 129 |
| ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 130 |
| ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 131 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24 |
| ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25 |
| ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26 |
| ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_1024 = S_MOV_B32 00 |
| %0.sub1:sgpr_1024 = S_MOV_B32 01 |
| %0.sub2:sgpr_1024 = S_MOV_B32 02 |
| %0.sub3:sgpr_1024 = S_MOV_B32 03 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3 |
| |
| undef %1.sub28:sgpr_1024 = S_MOV_B32 128 |
| %1.sub29:sgpr_1024 = S_MOV_B32 129 |
| %1.sub30:sgpr_1024 = S_MOV_B32 130 |
| %1.sub31:sgpr_1024 = S_MOV_B32 131 |
| S_NOP 0, implicit %1.sub28_sub29_sub30_sub31 |
| |
| undef %2.sub4:sgpr_1024 = S_MOV_B32 24 |
| %2.sub5:sgpr_1024 = S_MOV_B32 25 |
| %2.sub6:sgpr_1024 = S_MOV_B32 26 |
| %2.sub7:sgpr_1024 = S_MOV_B32 27 |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7 |
| |
| ... |
| # Skip test_sgpr_1024_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_1024 |
| # Skip test_sgpr_1024_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_1024 |
| --- |
| name: test_sgpr_1024_w256 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_1024_w256 |
| ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3 |
| ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4 |
| ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5 |
| ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6 |
| ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 124 |
| ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 125 |
| ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 126 |
| ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 127 |
| ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 128 |
| ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 129 |
| ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 130 |
| ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 131 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 24 |
| ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 25 |
| ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 26 |
| ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 27 |
| ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 28 |
| ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 29 |
| ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 210 |
| ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 211 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_1024 = S_MOV_B32 00 |
| %0.sub1:sgpr_1024 = S_MOV_B32 01 |
| %0.sub2:sgpr_1024 = S_MOV_B32 02 |
| %0.sub3:sgpr_1024 = S_MOV_B32 03 |
| %0.sub4:sgpr_1024 = S_MOV_B32 04 |
| %0.sub5:sgpr_1024 = S_MOV_B32 05 |
| %0.sub6:sgpr_1024 = S_MOV_B32 06 |
| %0.sub7:sgpr_1024 = S_MOV_B32 07 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 |
| |
| undef %1.sub24:sgpr_1024 = S_MOV_B32 124 |
| %1.sub25:sgpr_1024 = S_MOV_B32 125 |
| %1.sub26:sgpr_1024 = S_MOV_B32 126 |
| %1.sub27:sgpr_1024 = S_MOV_B32 127 |
| %1.sub28:sgpr_1024 = S_MOV_B32 128 |
| %1.sub29:sgpr_1024 = S_MOV_B32 129 |
| %1.sub30:sgpr_1024 = S_MOV_B32 130 |
| %1.sub31:sgpr_1024 = S_MOV_B32 131 |
| S_NOP 0, implicit %1.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| undef %2.sub4:sgpr_1024 = S_MOV_B32 24 |
| %2.sub5:sgpr_1024 = S_MOV_B32 25 |
| %2.sub6:sgpr_1024 = S_MOV_B32 26 |
| %2.sub7:sgpr_1024 = S_MOV_B32 27 |
| %2.sub8:sgpr_1024 = S_MOV_B32 28 |
| %2.sub9:sgpr_1024 = S_MOV_B32 29 |
| %2.sub10:sgpr_1024 = S_MOV_B32 210 |
| %2.sub11:sgpr_1024 = S_MOV_B32 211 |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11 |
| |
| ... |
| --- |
| name: test_sgpr_1024_w512 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: test_sgpr_1024_w512 |
| ; CHECK: undef %3.sub0:sgpr_512 = S_MOV_B32 0 |
| ; CHECK-NEXT: %3.sub1:sgpr_512 = S_MOV_B32 1 |
| ; CHECK-NEXT: %3.sub2:sgpr_512 = S_MOV_B32 2 |
| ; CHECK-NEXT: %3.sub3:sgpr_512 = S_MOV_B32 3 |
| ; CHECK-NEXT: %3.sub4:sgpr_512 = S_MOV_B32 4 |
| ; CHECK-NEXT: %3.sub5:sgpr_512 = S_MOV_B32 5 |
| ; CHECK-NEXT: %3.sub6:sgpr_512 = S_MOV_B32 6 |
| ; CHECK-NEXT: %3.sub7:sgpr_512 = S_MOV_B32 7 |
| ; CHECK-NEXT: %3.sub8:sgpr_512 = S_MOV_B32 8 |
| ; CHECK-NEXT: %3.sub9:sgpr_512 = S_MOV_B32 9 |
| ; CHECK-NEXT: %3.sub10:sgpr_512 = S_MOV_B32 10 |
| ; CHECK-NEXT: %3.sub11:sgpr_512 = S_MOV_B32 11 |
| ; CHECK-NEXT: %3.sub12:sgpr_512 = S_MOV_B32 12 |
| ; CHECK-NEXT: %3.sub13:sgpr_512 = S_MOV_B32 13 |
| ; CHECK-NEXT: %3.sub14:sgpr_512 = S_MOV_B32 14 |
| ; CHECK-NEXT: %3.sub15:sgpr_512 = S_MOV_B32 15 |
| ; CHECK-NEXT: S_NOP 0, implicit %3 |
| ; CHECK-NEXT: undef %4.sub0:sgpr_512 = S_MOV_B32 116 |
| ; CHECK-NEXT: %4.sub1:sgpr_512 = S_MOV_B32 117 |
| ; CHECK-NEXT: %4.sub2:sgpr_512 = S_MOV_B32 118 |
| ; CHECK-NEXT: %4.sub3:sgpr_512 = S_MOV_B32 119 |
| ; CHECK-NEXT: %4.sub4:sgpr_512 = S_MOV_B32 120 |
| ; CHECK-NEXT: %4.sub5:sgpr_512 = S_MOV_B32 121 |
| ; CHECK-NEXT: %4.sub6:sgpr_512 = S_MOV_B32 122 |
| ; CHECK-NEXT: %4.sub7:sgpr_512 = S_MOV_B32 123 |
| ; CHECK-NEXT: %4.sub8:sgpr_512 = S_MOV_B32 124 |
| ; CHECK-NEXT: %4.sub9:sgpr_512 = S_MOV_B32 125 |
| ; CHECK-NEXT: %4.sub10:sgpr_512 = S_MOV_B32 126 |
| ; CHECK-NEXT: %4.sub11:sgpr_512 = S_MOV_B32 127 |
| ; CHECK-NEXT: %4.sub12:sgpr_512 = S_MOV_B32 128 |
| ; CHECK-NEXT: %4.sub13:sgpr_512 = S_MOV_B32 129 |
| ; CHECK-NEXT: %4.sub14:sgpr_512 = S_MOV_B32 130 |
| ; CHECK-NEXT: %4.sub15:sgpr_512 = S_MOV_B32 131 |
| ; CHECK-NEXT: S_NOP 0, implicit %4 |
| ; CHECK-NEXT: undef %5.sub0:sgpr_512 = S_MOV_B32 24 |
| ; CHECK-NEXT: %5.sub1:sgpr_512 = S_MOV_B32 25 |
| ; CHECK-NEXT: %5.sub2:sgpr_512 = S_MOV_B32 26 |
| ; CHECK-NEXT: %5.sub3:sgpr_512 = S_MOV_B32 27 |
| ; CHECK-NEXT: %5.sub4:sgpr_512 = S_MOV_B32 28 |
| ; CHECK-NEXT: %5.sub5:sgpr_512 = S_MOV_B32 29 |
| ; CHECK-NEXT: %5.sub6:sgpr_512 = S_MOV_B32 210 |
| ; CHECK-NEXT: %5.sub7:sgpr_512 = S_MOV_B32 211 |
| ; CHECK-NEXT: %5.sub8:sgpr_512 = S_MOV_B32 212 |
| ; CHECK-NEXT: %5.sub9:sgpr_512 = S_MOV_B32 213 |
| ; CHECK-NEXT: %5.sub10:sgpr_512 = S_MOV_B32 214 |
| ; CHECK-NEXT: %5.sub11:sgpr_512 = S_MOV_B32 215 |
| ; CHECK-NEXT: %5.sub12:sgpr_512 = S_MOV_B32 216 |
| ; CHECK-NEXT: %5.sub13:sgpr_512 = S_MOV_B32 217 |
| ; CHECK-NEXT: %5.sub14:sgpr_512 = S_MOV_B32 218 |
| ; CHECK-NEXT: %5.sub15:sgpr_512 = S_MOV_B32 219 |
| ; CHECK-NEXT: S_NOP 0, implicit %5 |
| undef %0.sub0:sgpr_1024 = S_MOV_B32 00 |
| %0.sub1:sgpr_1024 = S_MOV_B32 01 |
| %0.sub2:sgpr_1024 = S_MOV_B32 02 |
| %0.sub3:sgpr_1024 = S_MOV_B32 03 |
| %0.sub4:sgpr_1024 = S_MOV_B32 04 |
| %0.sub5:sgpr_1024 = S_MOV_B32 05 |
| %0.sub6:sgpr_1024 = S_MOV_B32 06 |
| %0.sub7:sgpr_1024 = S_MOV_B32 07 |
| %0.sub8:sgpr_1024 = S_MOV_B32 08 |
| %0.sub9:sgpr_1024 = S_MOV_B32 09 |
| %0.sub10:sgpr_1024 = S_MOV_B32 010 |
| %0.sub11:sgpr_1024 = S_MOV_B32 011 |
| %0.sub12:sgpr_1024 = S_MOV_B32 012 |
| %0.sub13:sgpr_1024 = S_MOV_B32 013 |
| %0.sub14:sgpr_1024 = S_MOV_B32 014 |
| %0.sub15:sgpr_1024 = S_MOV_B32 015 |
| S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 |
| |
| undef %1.sub16:sgpr_1024 = S_MOV_B32 116 |
| %1.sub17:sgpr_1024 = S_MOV_B32 117 |
| %1.sub18:sgpr_1024 = S_MOV_B32 118 |
| %1.sub19:sgpr_1024 = S_MOV_B32 119 |
| %1.sub20:sgpr_1024 = S_MOV_B32 120 |
| %1.sub21:sgpr_1024 = S_MOV_B32 121 |
| %1.sub22:sgpr_1024 = S_MOV_B32 122 |
| %1.sub23:sgpr_1024 = S_MOV_B32 123 |
| %1.sub24:sgpr_1024 = S_MOV_B32 124 |
| %1.sub25:sgpr_1024 = S_MOV_B32 125 |
| %1.sub26:sgpr_1024 = S_MOV_B32 126 |
| %1.sub27:sgpr_1024 = S_MOV_B32 127 |
| %1.sub28:sgpr_1024 = S_MOV_B32 128 |
| %1.sub29:sgpr_1024 = S_MOV_B32 129 |
| %1.sub30:sgpr_1024 = S_MOV_B32 130 |
| %1.sub31:sgpr_1024 = S_MOV_B32 131 |
| S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31 |
| |
| undef %2.sub4:sgpr_1024 = S_MOV_B32 24 |
| %2.sub5:sgpr_1024 = S_MOV_B32 25 |
| %2.sub6:sgpr_1024 = S_MOV_B32 26 |
| %2.sub7:sgpr_1024 = S_MOV_B32 27 |
| %2.sub8:sgpr_1024 = S_MOV_B32 28 |
| %2.sub9:sgpr_1024 = S_MOV_B32 29 |
| %2.sub10:sgpr_1024 = S_MOV_B32 210 |
| %2.sub11:sgpr_1024 = S_MOV_B32 211 |
| %2.sub12:sgpr_1024 = S_MOV_B32 212 |
| %2.sub13:sgpr_1024 = S_MOV_B32 213 |
| %2.sub14:sgpr_1024 = S_MOV_B32 214 |
| %2.sub15:sgpr_1024 = S_MOV_B32 215 |
| %2.sub16:sgpr_1024 = S_MOV_B32 216 |
| %2.sub17:sgpr_1024 = S_MOV_B32 217 |
| %2.sub18:sgpr_1024 = S_MOV_B32 218 |
| %2.sub19:sgpr_1024 = S_MOV_B32 219 |
| S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19 |
| |
| ... |
