test/CodeGen/AMDGPU/pv-packing.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s

define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
; CHECK-LABEL: main:
; CHECK:       ; %bb.0: ; %main_body
; CHECK-NEXT:    CALL_FS
; CHECK-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
; CHECK-NEXT:    EXPORT T0.X___
; CHECK-NEXT:    CF_END
; CHECK-NEXT:    ALU clause starting at 4:
; CHECK-NEXT:     DOT4 T0.X, KC0[0].X, KC0[0].X,
; CHECK-NEXT:     DOT4 T0.Y (MASKED), KC0[0].Y, KC0[0].Y,
; CHECK-NEXT:     DOT4 T0.Z (MASKED), KC0[0].Z, KC0[0].Z,
; CHECK-NEXT:     DOT4 * T0.W (MASKED), KC0[0].W, KC0[0].W,
; CHECK-NEXT:     MULADD_IEEE T2.X, T1.X, T2.X, T3.X,
; CHECK-NEXT:     MULADD_IEEE T0.Y, T1.Y, T2.Y, T3.Y,
; CHECK-NEXT:     MULADD_IEEE T0.Z, T1.Z, T2.Z, T3.Z,
; CHECK-NEXT:     MULADD_IEEE * T0.W, PV.X, PV.X, T1.X, BS:VEC_120/SCL_212
; CHECK-NEXT:     DOT4 T0.X, T2.X, KC0[1].X,
; CHECK-NEXT:     DOT4 T0.Y (MASKED), T0.Y, KC0[1].Y,
; CHECK-NEXT:     DOT4 T0.Z (MASKED), T0.Z, KC0[1].Z,
; CHECK-NEXT:     DOT4 * T0.W (MASKED), T0.W, KC0[1].W,
main_body:
  %0 = extractelement <4 x float> %reg1, i32 0
  %1 = extractelement <4 x float> %reg1, i32 1
  %2 = extractelement <4 x float> %reg1, i32 2
  %3 = extractelement <4 x float> %reg2, i32 0
  %4 = extractelement <4 x float> %reg2, i32 1
  %5 = extractelement <4 x float> %reg2, i32 2
  %6 = extractelement <4 x float> %reg3, i32 0
  %7 = extractelement <4 x float> %reg3, i32 1
  %8 = extractelement <4 x float> %reg3, i32 2
  %9 = load <4 x float>, ptr addrspace(8) null
  %10 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 1)
  %11 = call float @llvm.r600.dot4(<4 x float> %9, <4 x float> %9)
  %12 = fmul float %0, %3
  %13 = fadd float %12, %6
  %14 = fmul float %1, %4
  %15 = fadd float %14, %7
  %16 = fmul float %2, %5
  %17 = fadd float %16, %8
  %18 = fmul float %11, %11
  %19 = fadd float %18, %0
  %20 = insertelement <4 x float> undef, float %13, i32 0
  %21 = insertelement <4 x float> %20, float %15, i32 1
  %22 = insertelement <4 x float> %21, float %17, i32 2
  %23 = insertelement <4 x float> %22, float %19, i32 3
  %24 = call float @llvm.r600.dot4(<4 x float> %23, <4 x float> %10)
  %25 = insertelement <4 x float> undef, float %24, i32 0
  call void @llvm.r600.store.swizzle(<4 x float> %25, i32 0, i32 2)
  ret void
}

; Function Attrs: readnone
declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1


declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)

attributes #1 = { readnone }