| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI %s |
| ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s |
| |
| define amdgpu_kernel void @s_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 { |
| ; SI-LABEL: s_bfm_pattern: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: s_bfm_b32 s2, s2, s3 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_mov_b32 s4, s0 |
| ; SI-NEXT: s_mov_b32 s5, s1 |
| ; SI-NEXT: v_mov_b32_e32 v0, s2 |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: s_bfm_pattern: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_bfm_b32 s2, s2, s3 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %a = shl i32 1, %x |
| %b = sub i32 %a, 1 |
| %c = shl i32 %b, %y |
| store i32 %c, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 { |
| ; SI-LABEL: s_bfm_pattern_simple: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dword s2, s[0:1], 0xb |
| ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; SI-NEXT: s_mov_b32 s3, 0xf000 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: s_bfm_b32 s4, s2, 0 |
| ; SI-NEXT: s_mov_b32 s2, -1 |
| ; SI-NEXT: v_mov_b32_e32 v0, s4 |
| ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: s_bfm_pattern_simple: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_bfm_b32 s2, s2, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %a = shl i32 1, %x |
| %b = sub i32 %a, 1 |
| store i32 %b, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 { |
| ; SI-LABEL: v_bfm_pattern: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, 0 |
| ; SI-NEXT: v_bfm_b32_e32 v2, v2, v3 |
| ; SI-NEXT: s_mov_b32 s4, s6 |
| ; SI-NEXT: s_mov_b32 s5, s6 |
| ; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 |
| ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) |
| ; SI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: v_bfm_pattern: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_bfm_b32 v2, v2, v3 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| %a = shl i32 1, %x |
| %b = sub i32 %a, 1 |
| %c = shl i32 %b, %y |
| store i32 %c, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 { |
| ; SI-LABEL: v_bfm_pattern_simple: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, 0 |
| ; SI-NEXT: v_bfm_b32_e64 v2, v2, 0 |
| ; SI-NEXT: s_mov_b32 s4, s6 |
| ; SI-NEXT: s_mov_b32 s5, s6 |
| ; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 |
| ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) |
| ; SI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: v_bfm_pattern_simple: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_bfm_b32 v2, v2, 0 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| %a = shl i32 1, %x |
| %b = sub i32 %a, 1 |
| store i32 %b, ptr addrspace(1) %out |
| ret void |
| } |
| |
| attributes #0 = { nounwind } |