test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: insert_lo32_i64_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_ss
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...

---
name: insert_lo32_i64_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $vgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_sv
    ; CHECK: liveins: $sgpr0_sgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_vs
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $sgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_vs
    ; CHECK: liveins: $vgpr0_vgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...

---
name: insert_lo32_i96_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
    ; CHECK-LABEL: name: insert_lo32_i96_v
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 0
    %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = COPY $vgpr3
    %2:_(s96) = G_INSERT %0, %1, 0
...

---
name: insert_lo32_i64_aa
legalized: true

body: |
  bb.0:
    liveins: $agpr0_agpr1, $agpr2
    ; CHECK-LABEL: name: insert_lo32_i64_aa
    ; CHECK: liveins: $agpr0_agpr1, $agpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:agpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
    %0:_(s64) = COPY $agpr0_agpr1
    %1:_(s32) = COPY $agpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...

---
name: insert_lo32_i64_av
legalized: true

body: |
  bb.0:
    liveins: $agpr0_agpr1, $vgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_av
    ; CHECK: liveins: $agpr0_agpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
    %0:_(s64) = COPY $agpr0_agpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_va
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $agpr2
    ; CHECK-LABEL: name: insert_lo32_i64_va
    ; CHECK: liveins: $vgpr0_vgpr1, $agpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $agpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...

---
name: insert_lo32_i64_as
legalized: true

body: |
  bb.0:
    liveins: $agpr0_agpr1, $sgpr2
    ; CHECK-LABEL: name: insert_lo32_i64_as
    ; CHECK: liveins: $agpr0_agpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
    %0:_(s64) = COPY $agpr0_agpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_sa
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $agpr2
    ; CHECK-LABEL: name: insert_lo32_i64_sa
    ; CHECK: liveins: $sgpr0_sgpr1, $agpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $agpr2
    %2:_(s64) = G_INSERT %0, %1, 0
...