test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s

# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+

---
name:            add_s16
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: add_s16
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6-NEXT: {{  $}}
    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
    ; GFX10-LABEL: name: add_s16
    ; GFX10: liveins: $vgpr0, $vgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s16) = G_TRUNC %0
    %3:vgpr(s16) = G_TRUNC %1
    %4:vgpr(s16) = G_ADD %2, %3
    S_ENDPGM 0, implicit %4

...

---
name:            add_s16_zext_to_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: add_s16_zext_to_s32
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6-NEXT: {{  $}}
    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
    ; GFX10-LABEL: name: add_s16_zext_to_s32
    ; GFX10: liveins: $vgpr0, $vgpr1
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ADD_NC_U16_e64_]], implicit $exec
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s16) = G_TRUNC %0
    %3:vgpr(s16) = G_TRUNC %1
    %4:vgpr(s16) = G_ADD %2, %3
    %5:vgpr(s32) = G_ZEXT %4
    S_ENDPGM 0, implicit %5

...

---
name:            add_s16_neg_inline_const_64
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GFX6-LABEL: name: add_s16_neg_inline_const_64
    ; GFX6: liveins: $vgpr0
    ; GFX6-NEXT: {{  $}}
    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
    ; GFX10-LABEL: name: add_s16_neg_inline_const_64
    ; GFX10: liveins: $vgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_CONSTANT i16 -64
    %3:vgpr(s16) = G_ADD %1, %2
    S_ENDPGM 0, implicit %3

...

---
name:            add_s16_neg_inline_const_64_zext_to_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
    ; GFX6: liveins: $vgpr0
    ; GFX6-NEXT: {{  $}}
    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
    ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
    ; GFX10: liveins: $vgpr0
    ; GFX10-NEXT: {{  $}}
    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
    ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
    ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_SUB_NC_U16_e64_]], implicit $exec
    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_CONSTANT i16 -64
    %3:vgpr(s16) = G_ADD %1, %2
    %4:vgpr(s32) = G_ZEXT %3
    S_ENDPGM 0, implicit %4

...