test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name: rotl_i32
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: rotl_i32
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt:_(s32) = COPY $vgpr1
    %bw:_(s32) = G_CONSTANT i32 32
    %shl:_(s32) = G_SHL %a, %amt
    %sub:_(s32) = G_SUB %bw, %amt
    %lshr:_(s32) = G_LSHR %a, %sub
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr2 = COPY %or
...

---
name: rotl_v2i32
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5

    ; CHECK-LABEL: name: rotl_v2i32
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: %amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
    ; CHECK-NEXT: %or:_(<2 x s32>) = G_ROTL %a, %amt(<2 x s32>)
    ; CHECK-NEXT: $vgpr4_vgpr5 = COPY %or(<2 x s32>)
    %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
    %scalar_bw:_(s32) = G_CONSTANT i32 32
    %bw:_(<2 x s32>) = G_BUILD_VECTOR %scalar_bw, %scalar_bw
    %shl:_(<2 x s32>) = G_SHL %a, %amt
    %sub:_(<2 x s32>) = G_SUB %bw, %amt
    %lshr:_(<2 x s32>) = G_LSHR %a, %sub
    %or:_(<2 x s32>) = G_OR %shl, %lshr
    $vgpr4_vgpr5 = COPY %or
...

---
name: rotl_commute_i32
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: rotl_commute_i32
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt:_(s32) = COPY $vgpr1
    %bw:_(s32) = G_CONSTANT i32 32
    %shl:_(s32) = G_SHL %a, %amt
    %sub:_(s32) = G_SUB %bw, %amt
    %lshr:_(s32) = G_LSHR %a, %sub
    %or:_(s32) = G_OR %lshr, %shl
    $vgpr2 = COPY %or
...

---
name: rotr_i32
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: rotr_i32
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt(s32)
    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt:_(s32) = COPY $vgpr1
    %bw:_(s32) = G_CONSTANT i32 32
    %lshr:_(s32) = G_LSHR %a, %amt
    %sub:_(s32) = G_SUB %bw, %amt
    %shl:_(s32) = G_SHL %a, %sub
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr2 = COPY %or
...

---
name: rot_i32_const
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: rot_i32_const
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 12
    ; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt1(s32)
    ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt0:_(s32) = G_CONSTANT i32 20
    %amt1:_(s32) = G_CONSTANT i32 12
    %shl:_(s32) = G_SHL %a, %amt0
    %lshr:_(s32) = G_LSHR %a, %amt1
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr1 = COPY %or
...

---
name: rot_v2i32_const
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: rot_v2i32_const
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: %scalar_amt1:_(s32) = G_CONSTANT i32 12
    ; CHECK-NEXT: %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1(s32), %scalar_amt1(s32)
    ; CHECK-NEXT: %or:_(<2 x s32>) = G_ROTR %a, %amt1(<2 x s32>)
    ; CHECK-NEXT: $vgpr2_vgpr3 = COPY %or(<2 x s32>)
    %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %scalar_amt0:_(s32) = G_CONSTANT i32 20
    %amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0, %scalar_amt0
    %scalar_amt1:_(s32) = G_CONSTANT i32 12
    %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1, %scalar_amt1
    %shl:_(<2 x s32>) = G_SHL %a, %amt0
    %lshr:_(<2 x s32>) = G_LSHR %a, %amt1
    %or:_(<2 x s32>) = G_OR %shl, %lshr
    $vgpr2_vgpr3 = COPY %or
...

---
name: rot_i32_bad_const
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: rot_i32_bad_const
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt0:_(s32) = G_CONSTANT i32 20
    ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 11
    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt0(s32)
    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %amt1(s32)
    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
    ; CHECK-NEXT: $vgpr1 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt0:_(s32) = G_CONSTANT i32 20
    %amt1:_(s32) = G_CONSTANT i32 11
    %shl:_(s32) = G_SHL %a, %amt0
    %lshr:_(s32) = G_LSHR %a, %amt1
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr1 = COPY %or
...


---
name: rotl_i32_bad_bw
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: rotl_i32_bad_bw
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
    ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
    ; CHECK-NEXT: $vgpr2 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt:_(s32) = COPY $vgpr1
    %bw:_(s32) = G_CONSTANT i32 31
    %shl:_(s32) = G_SHL %a, %amt
    %sub:_(s32) = G_SUB %bw, %amt
    %lshr:_(s32) = G_LSHR %a, %sub
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr2 = COPY %or
...

---
name: rotl_i32_bad_amt_reg
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3

    ; CHECK-LABEL: name: rotl_i32_bad_amt_reg
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr2
    ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
    ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
    ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
    ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
    ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
    ; CHECK-NEXT: $vgpr3 = COPY %or(s32)
    %a:_(s32) = COPY $vgpr0
    %amt:_(s32) = COPY $vgpr1
    %amt1:_(s32) = COPY $vgpr2
    %bw:_(s32) = G_CONSTANT i32 32
    %shl:_(s32) = G_SHL %a, %amt
    %sub:_(s32) = G_SUB %bw, %amt1
    %lshr:_(s32) = G_LSHR %a, %sub
    %or:_(s32) = G_OR %shl, %lshr
    $vgpr3 = COPY %or
...