[LoopUnroll] Regenerate test checks (NFC)
GitOrigin-RevId: c456ab78ae3aa9791e6137c06f30cc55f45a7cb2
diff --git a/test/Transforms/LoopUnroll/scevunroll.ll b/test/Transforms/LoopUnroll/scevunroll.ll
index ea473e1..4d9ae39 100644
--- a/test/Transforms/LoopUnroll/scevunroll.ll
+++ b/test/Transforms/LoopUnroll/scevunroll.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -S -indvars -loop-unroll -verify-loop-info | FileCheck %s
;
; Unit tests for loop unrolling using ScalarEvolution to compute trip counts.
@@ -6,12 +7,41 @@
; tests may check that SCEV is properly invalidated between passes.
; Completely unroll loops without a canonical IV.
-;
-; CHECK-LABEL: @sansCanonical(
-; CHECK-NOT: phi
-; CHECK-NOT: icmp
-; CHECK: ret
define i32 @sansCanonical(i32* %base) nounwind {
+; CHECK-LABEL: @sansCanonical(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 0 to i64
+; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
+; CHECK: while.body:
+; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[BASE:%.*]], i64 9
+; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[ADR]], align 8
+; CHECK-NEXT: [[ADR_1:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 8
+; CHECK-NEXT: [[TMP_1:%.*]] = load i32, i32* [[ADR_1]], align 8
+; CHECK-NEXT: [[SUM_NEXT_1:%.*]] = add i32 [[TMP]], [[TMP_1]]
+; CHECK-NEXT: [[ADR_2:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 7
+; CHECK-NEXT: [[TMP_2:%.*]] = load i32, i32* [[ADR_2]], align 8
+; CHECK-NEXT: [[SUM_NEXT_2:%.*]] = add i32 [[SUM_NEXT_1]], [[TMP_2]]
+; CHECK-NEXT: [[ADR_3:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 6
+; CHECK-NEXT: [[TMP_3:%.*]] = load i32, i32* [[ADR_3]], align 8
+; CHECK-NEXT: [[SUM_NEXT_3:%.*]] = add i32 [[SUM_NEXT_2]], [[TMP_3]]
+; CHECK-NEXT: [[ADR_4:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 5
+; CHECK-NEXT: [[TMP_4:%.*]] = load i32, i32* [[ADR_4]], align 8
+; CHECK-NEXT: [[SUM_NEXT_4:%.*]] = add i32 [[SUM_NEXT_3]], [[TMP_4]]
+; CHECK-NEXT: [[ADR_5:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 4
+; CHECK-NEXT: [[TMP_5:%.*]] = load i32, i32* [[ADR_5]], align 8
+; CHECK-NEXT: [[SUM_NEXT_5:%.*]] = add i32 [[SUM_NEXT_4]], [[TMP_5]]
+; CHECK-NEXT: [[ADR_6:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 3
+; CHECK-NEXT: [[TMP_6:%.*]] = load i32, i32* [[ADR_6]], align 8
+; CHECK-NEXT: [[SUM_NEXT_6:%.*]] = add i32 [[SUM_NEXT_5]], [[TMP_6]]
+; CHECK-NEXT: [[ADR_7:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 2
+; CHECK-NEXT: [[TMP_7:%.*]] = load i32, i32* [[ADR_7]], align 8
+; CHECK-NEXT: [[SUM_NEXT_7:%.*]] = add i32 [[SUM_NEXT_6]], [[TMP_7]]
+; CHECK-NEXT: [[ADR_8:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 1
+; CHECK-NEXT: [[TMP_8:%.*]] = load i32, i32* [[ADR_8]], align 8
+; CHECK-NEXT: [[SUM_NEXT_8:%.*]] = add i32 [[SUM_NEXT_7]], [[TMP_8]]
+; CHECK-NEXT: [[TMP_9:%.*]] = load i32, i32* [[BASE]], align 8
+; CHECK-NEXT: ret i32 [[SUM_NEXT_8]]
+;
entry:
br label %while.body
@@ -34,12 +64,29 @@
; case, the computed trip count based on a canonical IV is *not* for a
; latch block. Canonical unrolling incorrectly unrolls it, but SCEV
; unrolling does not.
-;
-; CHECK-LABEL: @earlyLoopTest(
-; CHECK: tail:
-; CHECK-NOT: br
-; CHECK: br i1 %cmp2, label %loop, label %exit2
define i64 @earlyLoopTest(i64* %base) nounwind {
+; CHECK-LABEL: @earlyLoopTest(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[TAIL:%.*]] ]
+; CHECK-NEXT: [[S:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[S_NEXT:%.*]], [[TAIL]] ]
+; CHECK-NEXT: [[ADR:%.*]] = getelementptr i64, i64* [[BASE:%.*]], i64 [[IV]]
+; CHECK-NEXT: [[VAL:%.*]] = load i64, i64* [[ADR]], align 4
+; CHECK-NEXT: [[S_NEXT]] = add i64 [[S]], [[VAL]]
+; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[INC]], 4
+; CHECK-NEXT: br i1 [[CMP]], label [[TAIL]], label [[EXIT1:%.*]]
+; CHECK: tail:
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[VAL]], 0
+; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT2:%.*]]
+; CHECK: exit1:
+; CHECK-NEXT: [[S_LCSSA:%.*]] = phi i64 [ [[S]], [[LOOP]] ]
+; CHECK-NEXT: ret i64 [[S_LCSSA]]
+; CHECK: exit2:
+; CHECK-NEXT: [[S_NEXT_LCSSA1:%.*]] = phi i64 [ [[S_NEXT]], [[TAIL]] ]
+; CHECK-NEXT: ret i64 [[S_NEXT_LCSSA1]]
+;
entry:
br label %loop
@@ -65,13 +112,24 @@
}
; SCEV properly unrolls multi-exit loops.
-;
-; CHECK-LABEL: @multiExit(
-; CHECK: getelementptr i32, i32* %base, i32 %iv
-; CHECK-NEXT: load i32, i32*
-; CHECK: br i1 false, label %l2, label %exit1
-; CHECK: br i1 true, label %l1, label %exit2
define i32 @multiExit(i32* %base) nounwind {
+; CHECK-LABEL: @multiExit(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[L1:%.*]]
+; CHECK: l1:
+; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[L2:%.*]] ]
+; CHECK-NEXT: [[INC1]] = add nuw nsw i32 [[IV1]], 1
+; CHECK-NEXT: [[ADR:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i32 [[IV1]]
+; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
+; CHECK-NEXT: br i1 false, label [[L2]], label [[EXIT1:%.*]]
+; CHECK: l2:
+; CHECK-NEXT: br i1 true, label [[L1]], label [[EXIT2:%.*]]
+; CHECK: exit1:
+; CHECK-NEXT: ret i32 1
+; CHECK: exit2:
+; CHECK-NEXT: [[VAL_LCSSA1:%.*]] = phi i32 [ [[VAL]], [[L2]] ]
+; CHECK-NEXT: ret i32 [[VAL_LCSSA1]]
+;
entry:
br label %l1
l1:
@@ -97,12 +155,29 @@
; a known trip count, regardless of the early exit trip counts. The
; LoopUnroll utility uses this assumption to optimize the latch
; block's branch.
-;
-; CHECK-LABEL: @multiExitIncomplete(
-; CHECK: l3:
-; CHECK-NOT: br
-; CHECK: br i1 %cmp3, label %l1, label %exit3
define i32 @multiExitIncomplete(i32* %base) nounwind {
+; CHECK-LABEL: @multiExitIncomplete(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[L1:%.*]]
+; CHECK: l1:
+; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[L3:%.*]] ]
+; CHECK-NEXT: [[INC1]] = add nuw i32 [[IV1]], 1
+; CHECK-NEXT: [[ADR:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i32 [[IV1]]
+; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IV1]], 5
+; CHECK-NEXT: br i1 [[CMP1]], label [[L2:%.*]], label [[EXIT1:%.*]]
+; CHECK: l2:
+; CHECK-NEXT: br i1 true, label [[L3]], label [[EXIT2:%.*]]
+; CHECK: l3:
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[VAL]], 0
+; CHECK-NEXT: br i1 [[CMP3]], label [[L1]], label [[EXIT3:%.*]]
+; CHECK: exit1:
+; CHECK-NEXT: ret i32 1
+; CHECK: exit2:
+; CHECK-NEXT: ret i32 2
+; CHECK: exit3:
+; CHECK-NEXT: ret i32 3
+;
entry:
br label %l1
l1:
@@ -131,11 +206,19 @@
; When loop unroll merges a loop exit with one of its parent loop's
; exits, SCEV must forget its ExitNotTaken info.
-;
-; CHECK-LABEL: @nestedUnroll(
-; CHECK-NOT: br i1
-; CHECK: for.body87:
define void @nestedUnroll() nounwind {
+; CHECK-LABEL: @nestedUnroll(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_INC:%.*]]
+; CHECK: for.inc:
+; CHECK-NEXT: br label [[FOR_BODY38:%.*]]
+; CHECK: for.body38:
+; CHECK-NEXT: br label [[FOR_BODY43:%.*]]
+; CHECK: for.body43:
+; CHECK-NEXT: br label [[FOR_BODY87:%.*]]
+; CHECK: for.body87:
+; CHECK-NEXT: br label [[FOR_BODY87]]
+;
entry:
br label %for.inc
@@ -177,13 +260,23 @@
; iteration via the early exit. So loop unrolling cannot assume that
; the loop latch's exit count of zero is an upper bound on the number
; of iterations.
-;
-; CHECK-LABEL: @nsw_latch(
-; CHECK: for.body:
-; CHECK: %b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ]
-; CHECK: return:
-; CHECK: %b.03.lcssa = phi i32 [ 8, %for.body ], [ 0, %for.cond ]
define void @nsw_latch(i32* %a) nounwind {
+; CHECK-LABEL: @nsw_latch(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[B_03:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_COND:%.*]] ]
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B_03]], 0
+; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[B_03]], 8
+; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_COND]], label [[RETURN:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT: br i1 false, label [[RETURN]], label [[FOR_BODY]]
+; CHECK: return:
+; CHECK-NEXT: [[B_03_LCSSA:%.*]] = phi i32 [ 8, [[FOR_BODY]] ], [ 0, [[FOR_COND]] ]
+; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 1, [[FOR_BODY]] ], [ 0, [[FOR_COND]] ]
+; CHECK-NEXT: store i32 [[B_03_LCSSA]], i32* [[A:%.*]], align 4
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
