test/CodeGen/AArch64/clmul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+sve2 | FileCheck %s

define <vscale x 16 x i8> @clmul_nxv16i8_sve(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
; CHECK-LABEL: clmul_nxv16i8_sve:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pmul z0.b, z0.b, z1.b
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x i8> @llvm.clmul.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
  ret <vscale x 16 x i8> %a
}

define <16 x i8> @clmul_v16i8_neon(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: clmul_v16i8_neon:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pmul v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %a = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %x, <16 x i8> %y)
  ret <16 x i8> %a
}

define <8 x i8> @clmul_v8i8_neon(<8 x i8> %x, <8 x i8> %y) {
; CHECK-LABEL: clmul_v8i8_neon:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pmul v0.8b, v0.8b, v1.8b
; CHECK-NEXT:    ret
  %a = call <8 x i8> @llvm.clmul.v8i8(<8 x i8> %x, <8 x i8> %y)
  ret <8 x i8> %a
}