commit 999cf1ebdd357a42150f74702ec229b00af2aa03
author Hsiangkai Wang <kai.wang@sifive.com> Thu Feb 18 22:45:32 2021 +0800
committer Copybara-Service <copybara-worker@google.com> Fri Feb 19 03:31:55 2021 -0800
tree dfc9ac77729a2320d012aca70847435b8dcb395d
parent bdc2452394602fb88dddccd8b28a2c9d6087abc1

[RISCV] Fix typo. Use ValueType instead of LLVMType.

GitOrigin-RevId: 065a187f337f2a3204c69c2a73a65aad49a44be1

lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

diff --git a/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index a98bb0f..ea0e5f1 100644
--- a/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -65,7 +65,7 @@
             (store_instr reg_class:$rs2, BaseAddr:$rs1, avl, sew)>;
 }
 
-multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
+multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
                                         int sew,
                                         LMULInfo vlmul,
                                         VReg reg_class>