[RISCV] Remove redundant test cases for index segment store (7/8).
Differential Revision: https://reviews.llvm.org/D97025
GitOrigin-RevId: c2f27da7e7eb514c1e2cb283fe832281fb17819e
diff --git a/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
index 35255ce..a88f37c 100644
--- a/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
+++ b/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
@@ -33,37 +33,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
@@ -95,374 +64,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
@@ -492,97 +93,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -614,126 +124,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -765,155 +155,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -945,186 +186,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -1156,130 +217,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -1311,161 +248,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -1497,194 +279,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -1718,138 +312,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -1883,171 +345,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -2081,206 +378,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -2316,146 +413,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -2491,181 +448,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -2701,218 +483,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -2950,154 +520,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -3135,191 +557,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -3357,230 +594,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -3620,162 +633,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -3815,201 +672,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -4049,242 +711,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -4326,170 +752,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -4531,211 +793,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -4777,211 +834,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
@@ -5011,37 +863,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
@@ -5073,370 +894,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
@@ -5466,68 +923,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
@@ -5559,37 +954,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
@@ -5621,378 +985,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
@@ -6024,68 +1016,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
@@ -6119,39 +1049,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
@@ -6185,402 +1082,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
@@ -6614,161 +1115,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -6800,306 +1146,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -7131,35 +1177,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -7191,128 +1208,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -7344,316 +1239,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -7685,37 +1270,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -7747,136 +1301,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -7910,336 +1334,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -8273,39 +1367,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -8339,144 +1400,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -8512,356 +1435,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -8897,41 +1470,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -8967,152 +1505,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -9150,376 +1542,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -9557,43 +1579,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -9631,160 +1616,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -9824,396 +1655,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -10253,45 +1694,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -10331,168 +1733,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -10534,416 +1774,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -10985,47 +1815,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -11067,167 +1856,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -11259,184 +1887,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -11468,157 +1918,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -11648,130 +1947,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -11803,192 +1978,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -12020,161 +2009,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -12206,138 +2040,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -12371,204 +2073,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -12602,171 +2106,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -12800,146 +2139,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -12975,216 +2174,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -13220,181 +2209,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -13430,154 +2244,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -13615,228 +2281,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -13874,191 +2318,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -14096,162 +2355,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -14291,240 +2394,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -14564,201 +2433,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -14798,170 +2472,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -15003,252 +2513,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -15290,211 +2554,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -15536,35 +2595,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -15596,126 +2626,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -15747,155 +2657,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -15927,186 +2688,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -16138,130 +2719,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -16293,161 +2750,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -16479,194 +2781,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -16700,138 +2814,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -16865,171 +2847,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -17063,206 +2880,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -17298,146 +2915,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -17473,181 +2950,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -17683,218 +2985,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -17932,154 +3022,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -18117,191 +3059,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -18339,230 +3096,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -18602,162 +3135,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -18797,201 +3174,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -19031,242 +3213,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -19308,170 +3254,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -19513,211 +3295,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -19759,424 +3336,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -20268,465 +3427,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -20820,485 +3520,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -21398,481 +3619,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -21962,463 +3708,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -22512,485 +3801,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -23090,515 +3900,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -23704,545 +4005,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -24354,575 +4116,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -25040,605 +4233,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -25762,549 +4356,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -26398,370 +4449,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -26793,184 +4480,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -27002,157 +4511,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -27182,130 +4540,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -27337,192 +4571,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -27554,161 +4602,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -27740,138 +4633,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -27905,204 +4666,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -28136,171 +4699,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -28334,146 +4732,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -28509,216 +4767,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -28754,181 +4802,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -28964,154 +4837,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -29149,228 +4874,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -29408,191 +4911,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -29630,162 +4948,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -29825,240 +4987,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -30098,201 +5026,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -30332,170 +5065,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -30537,252 +5106,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -30824,211 +5147,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -31070,35 +5188,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -31130,126 +5219,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -31281,155 +5250,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -31461,186 +5281,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -31672,130 +5312,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -31827,161 +5343,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -32013,194 +5374,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -32234,138 +5407,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -32399,171 +5440,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -32597,206 +5473,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -32832,146 +5508,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -33007,181 +5543,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -33217,218 +5578,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -33466,154 +5615,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -33651,191 +5652,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -33873,230 +5689,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -34136,162 +5728,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -34331,201 +5767,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -34565,242 +5806,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -34842,170 +5847,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -35047,211 +5888,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -35293,366 +5929,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
@@ -35682,221 +5958,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
@@ -35928,217 +5989,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -36170,306 +6020,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -36501,35 +6051,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -36561,128 +6082,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -36714,316 +6113,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -37055,37 +6144,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -37117,136 +6175,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -37280,336 +6208,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -37643,39 +6241,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -37709,144 +6274,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -37882,356 +6309,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -38267,41 +6344,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -38337,152 +6379,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -38520,376 +6416,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -38927,43 +6453,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -39001,160 +6490,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -39194,396 +6529,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -39623,45 +6568,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -39701,168 +6607,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -39904,416 +6648,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -40355,47 +6689,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -40437,136 +6730,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -40598,306 +6761,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -40929,35 +6792,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -40989,128 +6823,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -41142,316 +6854,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -41483,37 +6885,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -41545,136 +6916,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -41708,336 +6949,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -42071,39 +6982,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -42137,144 +7015,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -42310,356 +7050,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -42695,41 +7085,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -42765,152 +7120,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -42948,376 +7157,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -43355,43 +7194,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -43429,160 +7231,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -43622,396 +7270,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -44051,45 +7309,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -44129,168 +7348,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -44332,416 +7389,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -44783,47 +7430,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -44865,169 +7471,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -45059,186 +7502,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -45270,157 +7533,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -45452,130 +7564,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -45607,192 +7595,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -45824,161 +7626,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -46010,138 +7657,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -46175,204 +7690,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -46406,171 +7723,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -46635,37 +7787,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
@@ -46697,374 +7818,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
@@ -47094,192 +7847,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -47311,188 +7878,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -47524,159 +7909,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -47708,35 +7940,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -47768,126 +7971,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -47919,155 +8002,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -48099,186 +8033,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -48310,130 +8064,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -48465,161 +8095,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -48651,194 +8126,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -48872,138 +8159,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -49037,171 +8192,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -49235,206 +8225,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -49470,146 +8260,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -49645,181 +8295,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -49855,218 +8330,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -50104,154 +8367,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -50289,191 +8404,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -50511,230 +8441,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -50774,162 +8480,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -50969,201 +8519,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -51203,242 +8558,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -51480,170 +8599,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -51685,211 +8640,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -51931,300 +8681,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -52256,306 +8712,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -52587,35 +8743,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -52647,128 +8774,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -52800,316 +8805,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -53141,37 +8836,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -53203,136 +8867,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -53366,336 +8900,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -53729,39 +8933,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -53795,144 +8966,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -53968,356 +9001,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -54353,41 +9036,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -54423,152 +9071,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -54606,376 +9108,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -55013,43 +9145,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -55087,160 +9182,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -55280,396 +9221,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -55709,45 +9260,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -55787,168 +9299,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -55990,416 +9340,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -56441,47 +9381,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -56523,76 +9422,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -56624,126 +9453,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -56775,155 +9484,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -56955,186 +9515,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -57166,130 +9546,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -57321,161 +9577,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -57507,194 +9608,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -57728,138 +9641,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -57893,171 +9674,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -58091,206 +9707,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -58326,146 +9742,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -58501,181 +9777,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -58711,218 +9812,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -58960,154 +9849,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -59145,191 +9886,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -59367,230 +9923,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -59630,162 +9962,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -59825,201 +10001,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -60059,242 +10040,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -60336,170 +10081,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -60541,211 +10122,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -60787,240 +10163,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -61052,126 +10194,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -61203,155 +10225,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -61383,186 +10256,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -61594,130 +10287,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -61749,161 +10318,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -61935,194 +10349,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -62156,138 +10382,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -62321,171 +10415,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -62519,206 +10448,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -62754,146 +10483,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -62929,181 +10518,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -63139,218 +10553,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -63388,154 +10590,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -63573,191 +10627,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -63795,230 +10664,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -64058,162 +10703,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -64253,201 +10742,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -64487,242 +10781,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
@@ -64764,170 +10822,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
@@ -64969,211 +10863,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
@@ -65215,424 +10904,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -65724,465 +10995,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -66276,485 +11088,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -66854,485 +11187,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
@@ -67426,341 +11280,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv4r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -67792,308 +11311,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -68125,35 +11342,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -68185,130 +11373,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -68340,316 +11404,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -68681,37 +11435,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -68743,136 +11466,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -68906,336 +11499,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -69269,39 +11532,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -69335,159 +11565,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -69519,184 +11596,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -69728,157 +11627,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -69908,130 +11656,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -70063,192 +11687,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -70280,161 +11718,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -70466,138 +11749,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -70631,204 +11782,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -70862,171 +11815,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -71060,146 +11848,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -71235,216 +11883,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -71480,181 +11918,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -71690,154 +11953,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -71875,228 +11990,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -72134,191 +12027,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -72356,162 +12064,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -72551,240 +12103,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -72824,201 +12142,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -73058,170 +12181,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -73263,252 +12222,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -73550,211 +12263,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -73796,95 +12304,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -73916,306 +12335,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -74247,35 +12366,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -74307,128 +12397,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -74460,316 +12428,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -74801,37 +12459,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -74863,136 +12490,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -75026,336 +12523,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -75389,39 +12556,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -75455,144 +12589,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -75628,356 +12624,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -76013,41 +12659,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -76083,152 +12694,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -76266,376 +12731,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -76673,43 +12768,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -76747,160 +12805,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -76940,396 +12844,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -77369,45 +12883,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -77447,168 +12922,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
@@ -77650,416 +12963,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
@@ -78101,47 +13004,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vmv1r.v v13, v8
-; CHECK-NEXT: vmv1r.v v14, v8
-; CHECK-NEXT: vmv1r.v v15, v8
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
@@ -78183,169 +13045,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v0
-; CHECK-NEXT: vmv1r.v v2, v0
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v1, v8
-; CHECK-NEXT: vmv1r.v v2, v1
-; CHECK-NEXT: vmv1r.v v3, v1
-; CHECK-NEXT: vmv1r.v v4, v1
-; CHECK-NEXT: vmv1r.v v5, v1
-; CHECK-NEXT: vmv1r.v v6, v1
-; CHECK-NEXT: vmv1r.v v7, v1
-; CHECK-NEXT: vmv1r.v v8, v1
-; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -78377,186 +13076,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -78588,157 +13107,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -78770,130 +13138,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -78925,192 +13169,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -79142,161 +13200,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
@@ -79328,138 +13231,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
@@ -79493,204 +13264,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
@@ -79724,171 +13297,6 @@
ret void
}
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT: vmv2r.v v10, v8
-; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vmv2r.v v14, v8
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v0, v8
-; CHECK-NEXT: vmv2r.v v2, v0
-; CHECK-NEXT: vmv2r.v v4, v0
-; CHECK-NEXT: vmv2r.v v6, v0
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
- ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv2r.v v2, v8
-; CHECK-NEXT: vmv2r.v v4, v2
-; CHECK-NEXT: vmv2r.v v6, v2
-; CHECK-NEXT: vmv2r.v v8, v2
-; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT: ret
-entry:
- tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
- ret void
-}
-
declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
