test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s

--- |

  define i32 @compute(i32 %a) {
  body:
    ret i32 %a
  }

  define i32 @func(i32 %a) {
  entry:
    %b = alloca i32
    store i32 %a, i32* %b
    br label %check

  check:
    %comp = icmp sle i32 %a, 10
    br i1 %comp, label %loop, label %exit

  loop:
    %c = load i32, i32* %b
    %d = call i32 @compute(i32 %c)
    %e = sub i32 %d, 1
    store i32 %e, i32* %b
    br label %check

  exit:
    ret i32 0
  }

...
---
name:            compute
tracksRegLiveness: true
body: |
  bb.0.body:
    liveins: %edi

    %eax = COPY killed %edi
    RETQ killed %eax
...
---
name:            func
tracksRegLiveness: true
frameInfo:
  stackSize:       24
  maxAlignment:    4
  adjustsStack:    true
  hasCalls:        true
fixedStack:
  # CHECK: [[@LINE+1]]:93: expected a named register
  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }
stack:
  - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
body: |
  bb.0.entry:
    successors: %bb.1.check
    liveins: %edi, %rbx

    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
    %ebx = COPY %edi
    MOV32mr %rsp, 1, _, 12, _, %ebx

  bb.1.check:
    successors: %bb.2.loop, %bb.3.exit
    liveins: %ebx

    CMP32ri8 %ebx, 10, implicit-def %eflags
    JG_1 %bb.3.exit, implicit killed %eflags
    JMP_1 %bb.2.loop

  bb.2.loop:
    successors: %bb.1.check
    liveins: %ebx

    %edi = MOV32rm %rsp, 1, _, 12, _
    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
    %eax = DEC32r killed %eax, implicit-def dead %eflags
    MOV32mr %rsp, 1, _, 12, _, killed %eax
    JMP_1 %bb.1.check

  bb.3.exit:
    %eax = MOV32r0 implicit-def dead %eflags
    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
    %rbx = POP64r implicit-def %rsp, implicit %rsp
    RETQ %eax
...