test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI
# RUN: llc -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s  -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT
--- |
  define void @test_frem_float() { ret void }
  define void @test_frem_double() { ret void }

  define void @test_fpow_float() { ret void }
  define void @test_fpow_double() { ret void }

  define void @test_fadd_float() { ret void }
  define void @test_fadd_double() { ret void }

  define void @test_fsub_float() { ret void }
  define void @test_fsub_double() { ret void }

  define void @test_fcmp_true_s32() { ret void }
  define void @test_fcmp_false_s32() { ret void }

  define void @test_fcmp_oeq_s32() { ret void }
  define void @test_fcmp_ogt_s32() { ret void }
  define void @test_fcmp_oge_s32() { ret void }
  define void @test_fcmp_olt_s32() { ret void }
  define void @test_fcmp_ole_s32() { ret void }
  define void @test_fcmp_ord_s32() { ret void }
  define void @test_fcmp_ugt_s32() { ret void }
  define void @test_fcmp_uge_s32() { ret void }
  define void @test_fcmp_ult_s32() { ret void }
  define void @test_fcmp_ule_s32() { ret void }
  define void @test_fcmp_une_s32() { ret void }
  define void @test_fcmp_uno_s32() { ret void }

  define void @test_fcmp_one_s32() { ret void }
  define void @test_fcmp_ueq_s32() { ret void }

  define void @test_fcmp_true_s64() { ret void }
  define void @test_fcmp_false_s64() { ret void }

  define void @test_fcmp_oeq_s64() { ret void }
  define void @test_fcmp_ogt_s64() { ret void }
  define void @test_fcmp_oge_s64() { ret void }
  define void @test_fcmp_olt_s64() { ret void }
  define void @test_fcmp_ole_s64() { ret void }
  define void @test_fcmp_ord_s64() { ret void }
  define void @test_fcmp_ugt_s64() { ret void }
  define void @test_fcmp_uge_s64() { ret void }
  define void @test_fcmp_ult_s64() { ret void }
  define void @test_fcmp_ule_s64() { ret void }
  define void @test_fcmp_une_s64() { ret void }
  define void @test_fcmp_uno_s64() { ret void }

  define void @test_fcmp_one_s64() { ret void }
  define void @test_fcmp_ueq_s64() { ret void }
...
---
name:            test_frem_float
# CHECK-LABEL: name: test_frem_float
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-NOT: G_FREM
    ; CHECK: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; HARD-DAG: %s0 = COPY [[X]]
    ; HARD-DAG: %s1 = COPY [[Y]]
    ; SOFT: BL $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
    ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
    ; CHECK: ADJCALLSTACKUP
    ; CHECK-NOT: G_FREM
    %2(s32) = G_FREM %0, %1
    ; CHECK: %r0 = COPY [[R]]
    %r0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0
...
---
name:            test_frem_double
# CHECK-LABEL: name: test_frem_double
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    ; The inputs may be in the wrong order (depending on the target's
    ; endianness), but that's orthogonal to what we're trying to test here.
    ; For soft float, we only need to check that the first value, received
    ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
    ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
    ; For hard float, the values need to end up in D0 and D1.
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
    %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    ; CHECK-NOT: G_FREM
    ; CHECK: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
    ; HARD-DAG: %d0 = COPY [[X]]
    ; HARD-DAG: %d1 = COPY [[Y]]
    ; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
    ; CHECK: ADJCALLSTACKUP
    ; CHECK-NOT: G_FREM
    %6(s64) = G_FREM %4, %5
    %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
    %r0 = COPY %7(s32)
    %r1 = COPY %8(s32)
    BX_RET 14, _, implicit %r0, implicit %r1
...
---
name:            test_fpow_float
# CHECK-LABEL: name: test_fpow_float
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-NOT: G_FPOW
    ; CHECK: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; HARD-DAG: %s0 = COPY [[X]]
    ; HARD-DAG: %s1 = COPY [[Y]]
    ; SOFT: BL $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
    ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
    ; CHECK: ADJCALLSTACKUP
    ; CHECK-NOT: G_FPOW
    %2(s32) = G_FPOW %0, %1
    ; CHECK: %r0 = COPY [[R]]
    %r0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0
...
---
name:            test_fpow_double
# CHECK-LABEL: name: test_fpow_double
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    ; The inputs may be in the wrong order (depending on the target's
    ; endianness), but that's orthogonal to what we're trying to test here.
    ; For soft float, we only need to check that the first value, received
    ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
    ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
    ; For hard float, the values need to end up in D0 and D1.
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
    %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    ; CHECK-NOT: G_FPOW
    ; CHECK: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
    ; HARD-DAG: %d0 = COPY [[X]]
    ; HARD-DAG: %d1 = COPY [[Y]]
    ; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
    ; CHECK: ADJCALLSTACKUP
    ; CHECK-NOT: G_FPOW
    %6(s64) = G_FPOW %4, %5
    %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
    %r0 = COPY %7(s32)
    %r1 = COPY %8(s32)
    BX_RET 14, _, implicit %r0, implicit %r1
...
---
name:            test_fadd_float
# CHECK-LABEL: name: test_fadd_float
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]]
    ; SOFT-NOT: G_FADD
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-NOT: G_FADD
    %2(s32) = G_FADD %0, %1
    ; CHECK: %r0 = COPY [[R]]
    %r0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0
...
---
name:            test_fadd_double
# CHECK-LABEL: name: test_fadd_double
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
    %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    ; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]]
    ; SOFT-NOT: G_FADD
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-NOT: G_FADD
    %6(s64) = G_FADD %4, %5
    ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
    %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
    %r0 = COPY %7(s32)
    %r1 = COPY %8(s32)
    BX_RET 14, _, implicit %r0, implicit %r1
...
---
name:            test_fsub_float
# CHECK-LABEL: name: test_fsub_float
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]]
    ; SOFT-NOT: G_FSUB
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-NOT: G_FSUB
    %2(s32) = G_FSUB %0, %1
    ; CHECK: %r0 = COPY [[R]]
    %r0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0
...
---
name:            test_fsub_double
# CHECK-LABEL: name: test_fsub_double
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
    %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]]
    ; SOFT-NOT: G_FSUB
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
    ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
    ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-NOT: G_FSUB
    %6(s64) = G_FSUB %4, %5
    ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
    %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
    %r0 = COPY %7(s32)
    %r1 = COPY %8(s32)
    BX_RET 14, _, implicit %r0, implicit %r1
...
---
name:            test_fcmp_true_s32
# CHECK-LABEL: name: test_fcmp_true_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(true), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_false_s32
# CHECK-LABEL: name: test_fcmp_false_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(false), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oeq_s32
# CHECK-LABEL: name: test_fcmp_oeq_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ogt_s32
# CHECK-LABEL: name: test_fcmp_ogt_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oge_s32
# CHECK-LABEL: name: test_fcmp_oge_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_olt_s32
# CHECK-LABEL: name: test_fcmp_olt_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ole_s32
# CHECK-LABEL: name: test_fcmp_ole_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ord_s32
# CHECK-LABEL: name: test_fcmp_ord_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ugt_s32
# CHECK-LABEL: name: test_fcmp_ugt_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uge_s32
# CHECK-LABEL: name: test_fcmp_uge_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ult_s32
# CHECK-LABEL: name: test_fcmp_ult_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ule_s32
# CHECK-LABEL: name: test_fcmp_ule_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_une_s32
# CHECK-LABEL: name: test_fcmp_une_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(une), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uno_s32
# CHECK-LABEL: name: test_fcmp_uno_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_one_s32
# CHECK-LABEL: name: test_fcmp_one_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(one), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ueq_s32
# CHECK-LABEL: name: test_fcmp_ueq_s32
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
    %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X]]
    ; SOFT-DAG: %r1 = COPY [[Y]]
    ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
    ; SOFT-NOT: G_FCMP
    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_true_s64
# CHECK-LABEL: name: test_fcmp_true_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(true), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_false_s64
# CHECK-LABEL: name: test_fcmp_false_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(false), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oeq_s64
# CHECK-LABEL: name: test_fcmp_oeq_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ogt_s64
# CHECK-LABEL: name: test_fcmp_ogt_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oge_s64
# CHECK-LABEL: name: test_fcmp_oge_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(oge), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_olt_s64
# CHECK-LABEL: name: test_fcmp_olt_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(olt), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ole_s64
# CHECK-LABEL: name: test_fcmp_ole_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ole), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ord_s64
# CHECK-LABEL: name: test_fcmp_ord_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ord), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ugt_s64
# CHECK-LABEL: name: test_fcmp_ugt_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uge_s64
# CHECK-LABEL: name: test_fcmp_uge_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(uge), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ult_s64
# CHECK-LABEL: name: test_fcmp_ult_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ult), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ule_s64
# CHECK-LABEL: name: test_fcmp_ule_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ule), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_une_s64
# CHECK-LABEL: name: test_fcmp_une_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(une), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uno_s64
# CHECK-LABEL: name: test_fcmp_uno_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(uno), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_one_s64
# CHECK-LABEL: name: test_fcmp_one_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(one), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ueq_s64
# CHECK-LABEL: name: test_fcmp_ueq_s64
legalized:       false
# CHECK: legalized: true
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = COPY %r2
    %3(s32) = COPY %r3
    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
    %4(s64) = G_MERGE_VALUES %0(s32), %1
    %5(s64) = G_MERGE_VALUES %2(s32), %3
    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
    %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
    ; SOFT-NOT: G_FCMP
    ; SOFT: ADJCALLSTACKDOWN
    ; SOFT-DAG: %r0 = COPY [[X0]]
    ; SOFT-DAG: %r1 = COPY [[X1]]
    ; SOFT-DAG: %r2 = COPY [[Y0]]
    ; SOFT-DAG: %r3 = COPY [[Y1]]
    ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
    ; SOFT: ADJCALLSTACKUP
    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
    ; SOFT-NOT: G_FCMP
    %7(s32) = G_ZEXT %6(s1)
    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
    %r0 = COPY %7(s32)
    ; CHECK: %r0 = COPY [[REXT]]
    BX_RET 14, _, implicit %r0
...