test/CodeGen/AArch64/GlobalISel/select-muladd.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @SMADDLrrr_gpr() { ret void }
...

---
name:            SMADDLrrr_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %w1, %w2

    ; CHECK-LABEL: name: SMADDLrrr_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY %w2
    ; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
    ; CHECK: %x0 = COPY [[SMADDLrrr]]
    %0(s64) = COPY %x0
    %1(s32) = COPY %w1
    %2(s32) = COPY %w2
    %3(s64) = G_SEXT %1
    %4(s64) = G_SEXT %2
    %5(s64) = G_MUL %3, %4
    %6(s64) = G_ADD %0, %5
    %x0 = COPY %6
...