test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_shift() {
  entry:
    ret void
  }
...

---
name:            test_shift
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s8) = G_TRUNC %0
    %3(s8) = G_TRUNC %1

    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
    ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC]], [[C1]]
    ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
    ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
    ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
    ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[SEXT2]]
    ; CHECK: %4:_(s8) = G_TRUNC [[RES32]]
    %4(s8) = G_ASHR %2, %3


    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 255
    ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
    ; CHECK: [[ZEXT:%.*]]:_(s32) = G_AND [[SRC]], [[C1]]
    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 255
    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
    ; CHECK: [[ZEXT2:%.*]]:_(s32) = G_AND [[SRC2]], [[C2]]
    ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT2]]
    ; CHECK: %5:_(s8) = G_TRUNC [[RES32]]
    %5(s8) = G_LSHR %2, %3

    ; CHECK: [[OP0:%.*]]:_(s32) = G_TRUNC %0
    ; CHECK: [[OP1:%.*]]:_(s32) = G_TRUNC %1
    ; CHECK: [[RES32:%.*]]:_(s32) = G_SHL [[OP0]], [[OP1]]
    ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[RES32]](s32)
    %6(s8) = G_SHL %2, %3
...