test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_urem_64() {
  entry:
    ret void
  }
  define void @test_srem_32() {
  entry:
    ret void
  }
  define void @test_srem_8() {
  entry:
    ret void
  }
  define void @test_frem() {
  entry:
    ret void
  }
...

---
name:            test_urem_64
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3

    ; CHECK-LABEL: name: test_urem_64
    ; CHECK: [[QUOT:%[0-9]+]]:_(s64) = G_UDIV %0, %1
    ; CHECK: [[PROD:%[0-9]+]]:_(s64) = G_MUL [[QUOT]], %1
    ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SUB %0, [[PROD]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_UREM %0, %1


...
---
name:            test_srem_32
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_srem_32
    ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC %0(s64)
    ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC %1(s64)
    ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[T1]], [[T2]]
    ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[DIV]], [[T2]]
    ; CHECK: [[RES:%.*]]:_(s32) = G_SUB [[T1]], [[MUL]]

    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %3(s32) = G_TRUNC %0
    %4(s32) = G_TRUNC %1
    %5(s32) = G_SREM %3, %4

...
---
name:            test_srem_8
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_srem_8

    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[SRC1:%.*]]:_(s32) = G_TRUNC %0(s64)
    ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC1]], [[C1]]
    ; CHECK: [[LHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
    ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
    ; CHECK: [[RHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
    ; CHECK: [[SDIV:%.*]]:_(s32) = G_SDIV [[LHS_SEXT]], [[RHS_SEXT]]
    ; CHECK: [[A:%.*]]:_(s32) = COPY [[SDIV]]
    ; CHECK: [[SRC3:%.*]]:_(s32) = G_TRUNC %1(s64)
    ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[A]], [[SRC3]]
    ; CHECK: [[SRC4:%.*]]:_(s32) = G_TRUNC %0(s64)
    ; CHECK: [[SRC5:%.*]]:_(s32) = COPY [[MUL]]
    ; CHECK: [[SUB:%.*]]:_(s32) = G_SUB [[SRC4]], [[SRC5]]
    ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[SUB]]

    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %6(s8) = G_TRUNC %0
    %7(s8) = G_TRUNC %1
    %8(s8) = G_SREM %6, %7
...
---
name:            test_frem
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_frem

    ; CHECK: %d0 = COPY %0
    ; CHECK: %d1 = COPY %1
    ; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
    ; CHECK: [[RES:%.*]]:_(s64) = COPY %d0
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_FREM %0, %1

    ; CHECK: %s0 = COPY %3
    ; CHECK: %s1 = COPY %4
    ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
    ; CHECK: [[RES:%.*]]:_(s32) = COPY %s0
    %3(s32) = G_TRUNC %0
    %4(s32) = G_TRUNC %1
    %5(s32) = G_FREM %3, %4