test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_legalize_merge_v3s32() {
    ret void
  }
...
---
name:            test_legalize_merge_v3s32
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body: |
  bb.0:
    liveins: %w0, %w1, %w2
    ; CHECK-LABEL: name: test_legalize_merge_v3s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
    ; CHECK: [[MV:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = COPY %w2
    %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32)
...