test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir

# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @sdiv_s32_gpr() { ret void }
...

---
# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
# CHECK-LABEL: name: sdiv_s32_gpr
name:            sdiv_s32_gpr
legalized:       true
regBankSelected: true

# CHECK:      registers:
# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

# CHECK:  body:
# CHECK:    %0 = COPY %w0
# CHECK:    %1 = COPY %w1
# CHECK:    %2 = SDIVWr %0, %1
body:             |
  bb.0:
    liveins: %w0, %w1

    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
    %w0 = COPY %2(s32)
...