test/CodeGen/MIR/X86/subregister-operands.mir

# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses subregisters in register operands
# correctly.

--- |

  define zeroext i1 @t(i1 %c) {
  entry:
    ret i1 %c
  }

...
---
name:            t
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr8 }
  - { id: 2, class: gr8 }
body: |
  bb.0.entry:
    liveins: %edi
    ; CHECK:      %0 = COPY %edi
    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
    %0 = COPY %edi
    %1 = COPY %0.sub_8bit
    %2 = AND8ri %1, 1, implicit-def %eflags
    %al = COPY %2
    RETQ %al
...