test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @test_add_s8() { ret void }
  define void @test_add_s16() { ret void }
  define void @test_add_s32() { ret void }

  define void @test_load_from_stack() { ret void }
...
---
name:            test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s8) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s8) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s8) = G_ADD %0, %1
    ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _

    %r0 = COPY %2(s8)
    ; CHECK: %r0 = COPY [[VREGSUM]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_add_s16
# CHECK-LABEL: name: test_add_s16
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s16) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s16) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s16) = G_ADD %0, %1
    ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _

    %r0 = COPY %2(s16)
    ; CHECK: %r0 = COPY [[VREGSUM]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s32) = G_ADD %0, %1
    ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _

    %r0 = COPY %2(s32)
    ; CHECK: %r0 = COPY [[VREGSUM]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
# CHECK-DAG: id: 3, class: gpr
fixedStack:
  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK: id: [[FRAME_INDEX:[0-9]+]], offset: 8
body:             |
  bb.0:
    liveins: %r0, %r1, %r2, %r3

    %0(p0) = G_FRAME_INDEX %fixed-stack.2
    ; CHECK: [[FIVREG:%[0-9]+]] = ADDri %fixed-stack.[[FRAME_INDEX]], 0, 14, _, _

    %1(s32) = G_LOAD %0(p0)
    ; CHECK: {{%[0-9]+}} = LDRi12 [[FIVREG]], 0, 14, _

    BX_RET 14, _
    ; CHECK: BX_RET 14, _
...