test/CodeGen/X86/vec_set-6.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+sse4.1 | FileCheck %s

define <4 x float> @test(float %a, float %b, float %c) nounwind {
; CHECK-LABEL: test:
; CHECK:       # BB#0:
; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]
; CHECK-NEXT:    retl
  %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1
  %tmp8 = insertelement <4 x float> %tmp, float %b, i32 2
  %tmp10 = insertelement <4 x float> %tmp8, float %c, i32 3
  ret <4 x float> %tmp10
}