| //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file implements the PPC specific subclass of TargetSubtargetInfo. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "PPCSubtarget.h" |
| #include "PPC.h" |
| #include "PPCRegisterInfo.h" |
| #include "llvm/CodeGen/MachineFunction.h" |
| #include "llvm/CodeGen/MachineScheduler.h" |
| #include "llvm/IR/Attributes.h" |
| #include "llvm/IR/GlobalValue.h" |
| #include "llvm/IR/Function.h" |
| #include "llvm/Support/Host.h" |
| #include "llvm/Support/TargetRegistry.h" |
| #include "llvm/Target/TargetMachine.h" |
| #include <cstdlib> |
| |
| #define GET_SUBTARGETINFO_TARGET_DESC |
| #define GET_SUBTARGETINFO_CTOR |
| #include "PPCGenSubtargetInfo.inc" |
| |
| using namespace llvm; |
| |
| PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, |
| const std::string &FS, bool is64Bit) |
| : PPCGenSubtargetInfo(TT, CPU, FS) |
| , IsPPC64(is64Bit) |
| , TargetTriple(TT) { |
| initializeEnvironment(); |
| resetSubtargetFeatures(CPU, FS); |
| } |
| |
| /// SetJITMode - This is called to inform the subtarget info that we are |
| /// producing code for the JIT. |
| void PPCSubtarget::SetJITMode() { |
| // JIT mode doesn't want lazy resolver stubs, it knows exactly where |
| // everything is. This matters for PPC64, which codegens in PIC mode without |
| // stubs. |
| HasLazyResolverStubs = false; |
| |
| // Calls to external functions need to use indirect calls |
| IsJITCodeModel = true; |
| } |
| |
| void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) { |
| AttributeSet FnAttrs = MF->getFunction()->getAttributes(); |
| Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex, |
| "target-cpu"); |
| Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex, |
| "target-features"); |
| std::string CPU = |
| !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : ""; |
| std::string FS = |
| !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : ""; |
| if (!FS.empty()) { |
| initializeEnvironment(); |
| resetSubtargetFeatures(CPU, FS); |
| } |
| } |
| |
| void PPCSubtarget::initializeEnvironment() { |
| StackAlignment = 16; |
| DarwinDirective = PPC::DIR_NONE; |
| HasMFOCRF = false; |
| Has64BitSupport = false; |
| Use64BitRegs = false; |
| HasAltivec = false; |
| HasQPX = false; |
| HasFCPSGN = false; |
| HasFSQRT = false; |
| HasFRE = false; |
| HasFRES = false; |
| HasFRSQRTE = false; |
| HasFRSQRTES = false; |
| HasRecipPrec = false; |
| HasSTFIWX = false; |
| HasLFIWAX = false; |
| HasFPRND = false; |
| HasFPCVT = false; |
| HasISEL = false; |
| HasPOPCNTD = false; |
| HasLDBRX = false; |
| IsBookE = false; |
| DeprecatedMFTB = false; |
| DeprecatedDST = false; |
| HasLazyResolverStubs = false; |
| IsJITCodeModel = false; |
| } |
| |
| void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { |
| // Determine default and user specified characteristics |
| std::string CPUName = CPU; |
| if (CPUName.empty()) |
| CPUName = "generic"; |
| #if (defined(__APPLE__) || defined(__linux__)) && \ |
| (defined(__ppc__) || defined(__powerpc__)) |
| if (CPUName == "generic") |
| CPUName = sys::getHostCPUName(); |
| #endif |
| |
| // Initialize scheduling itinerary for the specified CPU. |
| InstrItins = getInstrItineraryForCPU(CPUName); |
| |
| // Make sure 64-bit features are available when CPUname is generic |
| std::string FullFS = FS; |
| |
| // If we are generating code for ppc64, verify that options make sense. |
| if (IsPPC64) { |
| Has64BitSupport = true; |
| // Silently force 64-bit register use on ppc64. |
| Use64BitRegs = true; |
| if (!FullFS.empty()) |
| FullFS = "+64bit," + FullFS; |
| else |
| FullFS = "+64bit"; |
| } |
| |
| // Parse features string. |
| ParseSubtargetFeatures(CPUName, FullFS); |
| |
| // If the user requested use of 64-bit regs, but the cpu selected doesn't |
| // support it, ignore. |
| if (use64BitRegs() && !has64BitSupport()) |
| Use64BitRegs = false; |
| |
| // Set up darwin-specific properties. |
| if (isDarwin()) |
| HasLazyResolverStubs = true; |
| |
| // QPX requires a 32-byte aligned stack. Note that we need to do this if |
| // we're compiling for a BG/Q system regardless of whether or not QPX |
| // is enabled because external functions will assume this alignment. |
| if (hasQPX() || isBGQ()) |
| StackAlignment = 32; |
| |
| // Determine endianness. |
| IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); |
| } |
| |
| /// hasLazyResolverStub - Return true if accesses to the specified global have |
| /// to go through a dyld lazy resolution stub. This means that an extra load |
| /// is required to get the address of the global. |
| bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, |
| const TargetMachine &TM) const { |
| // We never have stubs if HasLazyResolverStubs=false or if in static mode. |
| if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) |
| return false; |
| // If symbol visibility is hidden, the extra load is not needed if |
| // the symbol is definitely defined in the current translation unit. |
| bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); |
| if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) |
| return false; |
| return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || |
| GV->hasCommonLinkage() || isDecl; |
| } |
| |
| bool PPCSubtarget::enablePostRAScheduler( |
| CodeGenOpt::Level OptLevel, |
| TargetSubtargetInfo::AntiDepBreakMode& Mode, |
| RegClassVector& CriticalPathRCs) const { |
| Mode = TargetSubtargetInfo::ANTIDEP_ALL; |
| |
| CriticalPathRCs.clear(); |
| |
| if (isPPC64()) |
| CriticalPathRCs.push_back(&PPC::G8RCRegClass); |
| else |
| CriticalPathRCs.push_back(&PPC::GPRCRegClass); |
| |
| return OptLevel >= CodeGenOpt::Default; |
| } |
| |
| // Embedded cores need aggressive scheduling. |
| static bool needsAggressiveScheduling(unsigned Directive) { |
| switch (Directive) { |
| default: return false; |
| case PPC::DIR_440: |
| case PPC::DIR_A2: |
| case PPC::DIR_E500mc: |
| case PPC::DIR_E5500: |
| return true; |
| } |
| } |
| |
| bool PPCSubtarget::enableMachineScheduler() const { |
| // Enable MI scheduling for the embedded cores. |
| // FIXME: Enable this for all cores (some additional modeling |
| // may be necessary). |
| return needsAggressiveScheduling(DarwinDirective); |
| } |
| |
| void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, |
| MachineInstr *begin, |
| MachineInstr *end, |
| unsigned NumRegionInstrs) const { |
| if (needsAggressiveScheduling(DarwinDirective)) { |
| Policy.OnlyTopDown = false; |
| Policy.OnlyBottomUp = false; |
| } |
| |
| // Spilling is generally expensive on all PPC cores, so always enable |
| // register-pressure tracking. |
| Policy.ShouldTrackPressure = true; |
| } |
| |
| bool PPCSubtarget::useAA() const { |
| // Use AA during code generation for the embedded cores. |
| return needsAggressiveScheduling(DarwinDirective); |
| } |
| |