| let isCodeGenOnly = 1 in { |
| /// Arithmetic Instructions (ALU Immediate) |
| def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd>, |
| ADDI_FM_MM<0xc>; |
| def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, |
| ADDI_FM_MM<0x4>; |
| def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, |
| SLTI_FM_MM<0x24>; |
| def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, |
| SLTI_FM_MM<0x2c>; |
| def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, |
| ADDI_FM_MM<0x34>; |
| def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, |
| ADDI_FM_MM<0x14>; |
| def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, |
| ADDI_FM_MM<0x1c>; |
| def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM; |
| |
| /// Arithmetic Instructions (3-Operand, R-Type) |
| def ADDu_MM : MMRel, ArithLogicR<"addu", CPURegsOpnd>, ADD_FM_MM<0, 0x150>; |
| def SUBu_MM : MMRel, ArithLogicR<"subu", CPURegsOpnd>, ADD_FM_MM<0, 0x1d0>; |
| def MUL_MM : MMRel, ArithLogicR<"mul", CPURegsOpnd>, ADD_FM_MM<0, 0x210>; |
| def ADD_MM : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM_MM<0, 0x110>; |
| def SUB_MM : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM_MM<0, 0x190>; |
| def SLT_MM : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM_MM<0, 0x350>; |
| def SLTu_MM : MMRel, SetCC_R<"sltu", setult, CPURegs>, |
| ADD_FM_MM<0, 0x390>; |
| def AND_MM : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, |
| ADD_FM_MM<0, 0x250>; |
| def OR_MM : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, |
| ADD_FM_MM<0, 0x290>; |
| def XOR_MM : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, |
| ADD_FM_MM<0, 0x310>; |
| def NOR_MM : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM_MM<0, 0x2d0>; |
| def MULT_MM : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, |
| MULT_FM_MM<0x22c>; |
| def MULTu_MM : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, |
| MULT_FM_MM<0x26c>; |
| |
| /// Shift Instructions |
| def SLL_MM : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd>, |
| SRA_FM_MM<0, 0>; |
| def SRL_MM : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd>, |
| SRA_FM_MM<0x40, 0>; |
| def SRA_MM : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd>, |
| SRA_FM_MM<0x80, 0>; |
| def SLLV_MM : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd>, |
| SRLV_FM_MM<0x10, 0>; |
| def SRLV_MM : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd>, |
| SRLV_FM_MM<0x50, 0>; |
| def SRAV_MM : MMRel, shift_rotate_reg<"srav", CPURegsOpnd>, |
| SRLV_FM_MM<0x90, 0>; |
| def ROTR_MM : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd>, |
| SRA_FM_MM<0xc0, 0>; |
| def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd>, |
| SRLV_FM_MM<0xd0, 0>; |
| |
| /// Load and Store Instructions - aligned |
| defm LB_MM : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM_MM<0x7>; |
| defm LBu_MM : LoadM<"lbu", CPURegs, zextloadi8>, MMRel, LW_FM_MM<0x5>; |
| defm LH_MM : LoadM<"lh", CPURegs, sextloadi16>, MMRel, LW_FM_MM<0xf>; |
| defm LHu_MM : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM_MM<0xd>; |
| defm LW_MM : LoadM<"lw", CPURegs>, MMRel, LW_FM_MM<0x3f>; |
| defm SB_MM : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM_MM<0x6>; |
| defm SH_MM : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM_MM<0xe>; |
| defm SW_MM : StoreM<"sw", CPURegs>, MMRel, LW_FM_MM<0x3e>; |
| } |
