| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| # |
| # Verify folding operations into G_ICMP. |
| # |
| # E.g cmn/adds folding: |
| # |
| # x = G_SUB 0, y |
| # G_ICMP intpred(something_safe) z, x |
| # |
| # Folds to: |
| # adds z, y |
| # |
| # Where "something_safe" is ne or eq. |
| # |
| # ands/tst folding: |
| # |
| # z = G_AND x, y |
| # G_ICMP z, 0 |
| # |
| # Folds to: |
| # |
| # tst x, y |
| # |
| # When we have signed comparisons. |
| # |
| # Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose |
| # names start with no_cmn should use SUBS. Similarly, tests whose names start |
| # with TST should use ANDS for the G_ICMP. |
| # |
| |
| ... |
| --- |
| name: cmn_s32_rhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: cmn_s32_rhs |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_SUB %2, %1 |
| %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: cmn_s32_lhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: cmn_s32_lhs |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_SUB %2, %0 |
| %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: no_cmn_s32_rhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: no_cmn_s32_rhs |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_SUB %2, %1 |
| %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: no_cmn_s32_lhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: no_cmn_s32_lhs |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv |
| ; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_SUB %2, %0 |
| %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: cmn_s64_rhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: cmn_s64_rhs |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 |
| ; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv |
| ; CHECK: $x0 = COPY [[CSELXr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %2:gpr(s64) = G_CONSTANT i64 0 |
| %6:gpr(s64) = G_CONSTANT i64 1 |
| %3:gpr(s64) = G_SUB %2, %1 |
| %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s64) = G_SELECT %4(s1), %6, %2 |
| $x0 = COPY %5(s64) |
| RET_ReallyLR implicit $x0 |
| |
| ... |
| --- |
| name: cmn_s64_lhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: cmn_s64_lhs |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 |
| ; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv |
| ; CHECK: $x0 = COPY [[CSELXr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %2:gpr(s64) = G_CONSTANT i64 0 |
| %6:gpr(s64) = G_CONSTANT i64 1 |
| %3:gpr(s64) = G_SUB %2, %0 |
| %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s64) = G_SELECT %4(s1), %6, %2 |
| $x0 = COPY %5(s64) |
| RET_ReallyLR implicit $x0 |
| |
| ... |
| --- |
| name: no_cmn_s64_rhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: no_cmn_s64_rhs |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 |
| ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv |
| ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv |
| ; CHECK: $x0 = COPY [[CSELXr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %2:gpr(s64) = G_CONSTANT i64 0 |
| %6:gpr(s64) = G_CONSTANT i64 1 |
| %3:gpr(s64) = G_SUB %2, %1 |
| %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s64) = G_SELECT %4(s1), %6, %2 |
| $x0 = COPY %5(s64) |
| RET_ReallyLR implicit $x0 |
| |
| ... |
| --- |
| name: no_cmn_s64_lhs |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: no_cmn_s64_lhs |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 |
| ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv |
| ; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv |
| ; CHECK: $x0 = COPY [[CSELXr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %2:gpr(s64) = G_CONSTANT i64 0 |
| %6:gpr(s64) = G_CONSTANT i64 1 |
| %3:gpr(s64) = G_SUB %2, %0 |
| %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s64) = G_SELECT %4(s1), %6, %2 |
| $x0 = COPY %5(s64) |
| RET_ReallyLR implicit $x0 |
| |
| ... |
| --- |
| name: tst_s32 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| ; CHECK-LABEL: name: tst_s32 |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: $wzr = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_AND %2, %1 |
| %8:gpr(s32) = G_CONSTANT i32 0 |
| %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: tst_s64 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| ; CHECK-LABEL: name: tst_s64 |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 |
| ; CHECK: $xzr = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv |
| ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv |
| ; CHECK: $x0 = COPY [[CSELXr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %2:gpr(s64) = G_CONSTANT i64 0 |
| %6:gpr(s64) = G_CONSTANT i64 1 |
| %3:gpr(s64) = G_AND %2, %1 |
| %8:gpr(s64) = G_CONSTANT i64 0 |
| %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s64) = G_SELECT %4(s1), %6, %2 |
| $x0 = COPY %5(s64) |
| RET_ReallyLR implicit $x0 |
| |
| ... |
| --- |
| name: no_tst_unsigned_compare |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| ; CHECK-LABEL: name: no_tst_unsigned_compare |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]] |
| ; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_AND %2, %1 |
| %8:gpr(s32) = G_CONSTANT i32 0 |
| %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: no_tst_nonzero |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| ; CHECK-LABEL: name: no_tst_nonzero |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]] |
| ; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv |
| ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSELWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %6:gpr(s32) = G_CONSTANT i32 1 |
| %3:gpr(s32) = G_AND %2, %1 |
| %8:gpr(s32) = G_CONSTANT i32 42 |
| %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8 |
| %4:gpr(s1) = G_TRUNC %7(s32) |
| %5:gpr(s32) = G_SELECT %4(s1), %6, %2 |
| $w0 = COPY %5(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: imm_tst |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| ; CHECK-LABEL: name: imm_tst |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: $wzr = ANDSWri [[COPY]], 1, implicit-def $nzcv |
| ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSINCWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %3:gpr(s32) = G_CONSTANT i32 1 |
| |
| ; This can be represented as a logical immediate, so we can pull it into |
| ; the ANDS. We should get ANDSWri. |
| %4:gpr(s32) = G_CONSTANT i32 3 |
| |
| %5:gpr(s32) = G_AND %1, %4 |
| %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2 |
| $w0 = COPY %6(s32) |
| RET_ReallyLR implicit $w0 |
| |
| |
| ... |
| --- |
| name: no_imm_tst_not_logical_imm |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| ; CHECK-LABEL: name: no_imm_tst_not_logical_imm |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1 |
| ; CHECK: $wzr = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv |
| ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSINCWr]] |
| ; CHECK: RET_ReallyLR implicit $w0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %3:gpr(s32) = G_CONSTANT i32 1 |
| |
| ; This immediate can't be represented as a logical immediate. We shouldn't |
| ; select ANDSWri. |
| %4:gpr(s32) = G_CONSTANT i32 -1 |
| |
| %5:gpr(s32) = G_AND %1, %4 |
| %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2 |
| $w0 = COPY %6(s32) |
| RET_ReallyLR implicit $w0 |
| |
| ... |
| --- |
| name: test_physreg_copy |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| ; CHECK-LABEL: name: test_physreg_copy |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv |
| ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv |
| ; CHECK: $w0 = COPY [[CSINCWr]] |
| ; CHECK: RET_ReallyLR implicit $x0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| ; When we find the defs of the LHS and RHS of the compare, we walk over |
| ; copies. Make sure that we don't crash when we hit a copy from a physical |
| ; register. |
| %7:gpr(s32) = G_ICMP intpred(eq), %0, %1 |
| $w0 = COPY %7(s32) |
| RET_ReallyLR implicit $x0 |