[Codegen] Adjust saturation test. NFC.
Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375009 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/AArch64/sadd_sat_plus.ll b/test/CodeGen/AArch64/sadd_sat_plus.ll
new file mode 100644
index 0000000..9531fcc
--- /dev/null
+++ b/test/CodeGen/AArch64/sadd_sat_plus.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-LABEL: func32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: adds w10, w0, w8
+; CHECK-NEXT: mov w9, #2147483647
+; CHECK-NEXT: cmp w10, #0 // =0
+; CHECK-NEXT: cinv w9, w9, ge
+; CHECK-NEXT: adds w8, w0, w8
+; CHECK-NEXT: csel w0, w9, w8, vs
+; CHECK-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-LABEL: func64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adds x8, x0, x2
+; CHECK-NEXT: mov x9, #9223372036854775807
+; CHECK-NEXT: cmp x8, #0 // =0
+; CHECK-NEXT: cinv x8, x9, ge
+; CHECK-NEXT: adds x9, x0, x2
+; CHECK-NEXT: csel x0, x8, x9, vs
+; CHECK-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; CHECK-LABEL: func16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #16
+; CHECK-NEXT: adds w11, w9, w8, lsl #16
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: adds w8, w9, w8, lsl #16
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #24
+; CHECK-NEXT: adds w11, w9, w8, lsl #24
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: adds w8, w9, w8, lsl #24
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #24
+; CHECK-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #28
+; CHECK-NEXT: adds w11, w9, w8, lsl #28
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: adds w8, w9, w8, lsl #28
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/AArch64/ssub_sat_plus.ll b/test/CodeGen/AArch64/ssub_sat_plus.ll
new file mode 100644
index 0000000..26bac69
--- /dev/null
+++ b/test/CodeGen/AArch64/ssub_sat_plus.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-LABEL: func32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: subs w10, w0, w8
+; CHECK-NEXT: mov w9, #2147483647
+; CHECK-NEXT: cmp w10, #0 // =0
+; CHECK-NEXT: cinv w9, w9, ge
+; CHECK-NEXT: subs w8, w0, w8
+; CHECK-NEXT: csel w0, w9, w8, vs
+; CHECK-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-LABEL: func64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x8, x0, x2
+; CHECK-NEXT: mov x9, #9223372036854775807
+; CHECK-NEXT: cmp x8, #0 // =0
+; CHECK-NEXT: cinv x8, x9, ge
+; CHECK-NEXT: subs x9, x0, x2
+; CHECK-NEXT: csel x0, x8, x9, vs
+; CHECK-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; CHECK-LABEL: func16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #16
+; CHECK-NEXT: subs w11, w9, w8, lsl #16
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: subs w8, w9, w8, lsl #16
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #24
+; CHECK-NEXT: subs w11, w9, w8, lsl #24
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: subs w8, w9, w8, lsl #24
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #24
+; CHECK-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #28
+; CHECK-NEXT: subs w11, w9, w8, lsl #28
+; CHECK-NEXT: mov w10, #2147483647
+; CHECK-NEXT: cmp w11, #0 // =0
+; CHECK-NEXT: cinv w10, w10, ge
+; CHECK-NEXT: subs w8, w9, w8, lsl #28
+; CHECK-NEXT: csel w8, w10, w8, vs
+; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/AArch64/uadd_sat_plus.ll b/test/CodeGen/AArch64/uadd_sat_plus.ll
new file mode 100644
index 0000000..2989fc5
--- /dev/null
+++ b/test/CodeGen/AArch64/uadd_sat_plus.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+declare i4 @llvm.uadd.sat.i4(i4, i4)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-LABEL: func32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: adds w8, w0, w8
+; CHECK-NEXT: csinv w0, w8, wzr, lo
+; CHECK-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-LABEL: func64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adds x8, x0, x2
+; CHECK-NEXT: csinv x0, x8, xzr, lo
+; CHECK-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; CHECK-LABEL: func16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #16
+; CHECK-NEXT: adds w8, w9, w8, lsl #16
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #24
+; CHECK-NEXT: adds w8, w9, w8, lsl #24
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #24
+; CHECK-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #28
+; CHECK-NEXT: adds w8, w9, w8, lsl #28
+; CHECK-NEXT: csinv w8, w8, wzr, lo
+; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/AArch64/usub_sat_plus.ll b/test/CodeGen/AArch64/usub_sat_plus.ll
new file mode 100644
index 0000000..c836941
--- /dev/null
+++ b/test/CodeGen/AArch64/usub_sat_plus.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+declare i4 @llvm.usub.sat.i4(i4, i4)
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare i16 @llvm.usub.sat.i16(i16, i16)
+declare i32 @llvm.usub.sat.i32(i32, i32)
+declare i64 @llvm.usub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-LABEL: func32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: subs w8, w0, w8
+; CHECK-NEXT: csel w0, wzr, w8, lo
+; CHECK-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-LABEL: func64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x8, x0, x2
+; CHECK-NEXT: csel x0, xzr, x8, lo
+; CHECK-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; CHECK-LABEL: func16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #16
+; CHECK-NEXT: subs w8, w9, w8, lsl #16
+; CHECK-NEXT: csel w8, wzr, w8, lo
+; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #24
+; CHECK-NEXT: subs w8, w9, w8, lsl #24
+; CHECK-NEXT: csel w8, wzr, w8, lo
+; CHECK-NEXT: lsr w0, w8, #24
+; CHECK-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w8, w1, w2
+; CHECK-NEXT: lsl w9, w0, #28
+; CHECK-NEXT: subs w8, w9, w8, lsl #28
+; CHECK-NEXT: csel w8, wzr, w8, lo
+; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/ARM/sadd_sat.ll b/test/CodeGen/ARM/sadd_sat.ll
index 387850c..e3d329c 100644
--- a/test/CodeGen/ARM/sadd_sat.ll
+++ b/test/CodeGen/ARM/sadd_sat.ll
@@ -207,7 +207,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r3, r1, #16
@@ -276,7 +276,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r3, r1, #24
@@ -345,7 +345,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r3, r1, #28
diff --git a/test/CodeGen/ARM/sadd_sat_plus.ll b/test/CodeGen/ARM/sadd_sat_plus.ll
new file mode 100644
index 0000000..8d41eb6
--- /dev/null
+++ b/test/CodeGen/ARM/sadd_sat_plus.ll
@@ -0,0 +1,433 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: mov r3, r0
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: mov r1, r2
+; CHECK-T1-NEXT: bmi .LBB0_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: .LBB0_2:
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: bne .LBB0_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r1, r2, #31
+; CHECK-T1-NEXT: cmp r0, r3
+; CHECK-T1-NEXT: bvs .LBB0_5
+; CHECK-T1-NEXT: b .LBB0_6
+; CHECK-T1-NEXT: .LBB0_4:
+; CHECK-T1-NEXT: ldr r1, .LCPI0_0
+; CHECK-T1-NEXT: cmp r0, r3
+; CHECK-T1-NEXT: bvc .LBB0_6
+; CHECK-T1-NEXT: .LBB0_5:
+; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: .LBB0_6:
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI0_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mla r2, r1, r2, r0
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r3, #1
+; CHECK-T2-NEXT: cmp r3, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r1, #-2147483648
+; CHECK-T2-NEXT: cmp r2, r0
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r1, r2
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mla r2, r1, r2, r0
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: movwmi r3, #1
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: mvnne r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r2, r0
+; CHECK-ARM-NEXT: movvc r1, r2
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT: .pad #4
+; CHECK-T1-NEXT: sub sp, #4
+; CHECK-T1-NEXT: ldr r5, [sp, #28]
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: cmp r5, #0
+; CHECK-T1-NEXT: mov r3, r2
+; CHECK-T1-NEXT: bge .LBB1_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: mov r3, r4
+; CHECK-T1-NEXT: .LBB1_2:
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: mov r6, r2
+; CHECK-T1-NEXT: bge .LBB1_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: mov r6, r4
+; CHECK-T1-NEXT: .LBB1_4:
+; CHECK-T1-NEXT: subs r7, r6, r3
+; CHECK-T1-NEXT: rsbs r3, r7, #0
+; CHECK-T1-NEXT: adcs r3, r7
+; CHECK-T1-NEXT: ldr r7, [sp, #24]
+; CHECK-T1-NEXT: adds r0, r0, r7
+; CHECK-T1-NEXT: adcs r1, r5
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: mov r5, r2
+; CHECK-T1-NEXT: bge .LBB1_6
+; CHECK-T1-NEXT: @ %bb.5:
+; CHECK-T1-NEXT: mov r5, r4
+; CHECK-T1-NEXT: .LBB1_6:
+; CHECK-T1-NEXT: subs r4, r6, r5
+; CHECK-T1-NEXT: subs r5, r4, #1
+; CHECK-T1-NEXT: sbcs r4, r5
+; CHECK-T1-NEXT: ands r3, r4
+; CHECK-T1-NEXT: beq .LBB1_8
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: asrs r0, r1, #31
+; CHECK-T1-NEXT: .LBB1_8:
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: bmi .LBB1_10
+; CHECK-T1-NEXT: @ %bb.9:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: beq .LBB1_11
+; CHECK-T1-NEXT: b .LBB1_12
+; CHECK-T1-NEXT: .LBB1_10:
+; CHECK-T1-NEXT: ldr r2, .LCPI1_0
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: bne .LBB1_12
+; CHECK-T1-NEXT: .LBB1_11:
+; CHECK-T1-NEXT: mov r2, r1
+; CHECK-T1-NEXT: .LBB1_12:
+; CHECK-T1-NEXT: mov r1, r2
+; CHECK-T1-NEXT: add sp, #4
+; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.13:
+; CHECK-T1-NEXT: .LCPI1_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: .save {r7, lr}
+; CHECK-T2-NEXT: push {r7, lr}
+; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8]
+; CHECK-T2-NEXT: cmp.w r1, #-1
+; CHECK-T2-NEXT: mov.w r3, #0
+; CHECK-T2-NEXT: mov.w lr, #0
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r3, #1
+; CHECK-T2-NEXT: adds r0, r0, r2
+; CHECK-T2-NEXT: adc.w r2, r1, r12
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp.w r2, #-1
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: subs r1, r3, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r1, #1
+; CHECK-T2-NEXT: cmp.w r12, #-1
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt.w lr, #1
+; CHECK-T2-NEXT: sub.w r3, r3, lr
+; CHECK-T2-NEXT: clz r3, r3
+; CHECK-T2-NEXT: lsrs r3, r3, #5
+; CHECK-T2-NEXT: ands r3, r1
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: asrne r0, r2, #31
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: mvnmi r1, #-2147483648
+; CHECK-T2-NEXT: cmp r3, #0
+; CHECK-T2-NEXT: it eq
+; CHECK-T2-NEXT: moveq r1, r2
+; CHECK-T2-NEXT: pop {r7, pc}
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: .save {r11, lr}
+; CHECK-ARM-NEXT: push {r11, lr}
+; CHECK-ARM-NEXT: ldr r2, [sp, #8]
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: ldr r12, [sp, #12]
+; CHECK-ARM-NEXT: adds r0, r0, r2
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: adc lr, r1, r12
+; CHECK-ARM-NEXT: cmn r1, #1
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: cmn lr, #1
+; CHECK-ARM-NEXT: movwgt r2, #1
+; CHECK-ARM-NEXT: subs r2, r1, r2
+; CHECK-ARM-NEXT: movwne r2, #1
+; CHECK-ARM-NEXT: cmn r12, #1
+; CHECK-ARM-NEXT: movwgt r3, #1
+; CHECK-ARM-NEXT: sub r1, r1, r3
+; CHECK-ARM-NEXT: clz r1, r1
+; CHECK-ARM-NEXT: lsr r1, r1, #5
+; CHECK-ARM-NEXT: ands r2, r1, r2
+; CHECK-ARM-NEXT: asrne r0, lr, #31
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: cmp lr, #0
+; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: moveq r1, lr
+; CHECK-ARM-NEXT: pop {r11, pc}
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r3, r1, #16
+; CHECK-T1-NEXT: lsls r1, r0, #16
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: adds r0, r1, r3
+; CHECK-T1-NEXT: mov r3, r2
+; CHECK-T1-NEXT: bmi .LBB2_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: .LBB2_2:
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: bne .LBB2_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvs .LBB2_5
+; CHECK-T1-NEXT: b .LBB2_6
+; CHECK-T1-NEXT: .LBB2_4:
+; CHECK-T1-NEXT: ldr r2, .LCPI2_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvc .LBB2_6
+; CHECK-T1-NEXT: .LBB2_5:
+; CHECK-T1-NEXT: mov r0, r2
+; CHECK-T1-NEXT: .LBB2_6:
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI2_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #16
+; CHECK-T2-NEXT: mov.w r3, #-2147483648
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #16
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp r1, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r2, #1
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r3, #-2147483648
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #16
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r3, r1
+; CHECK-T2-NEXT: asrs r0, r3, #16
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #16
+; CHECK-ARM-NEXT: mov r3, #-2147483648
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #16
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r1, #0
+; CHECK-ARM-NEXT: movwmi r2, #1
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: mvnne r3, #-2147483648
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #16
+; CHECK-ARM-NEXT: movvc r3, r1
+; CHECK-ARM-NEXT: asr r0, r3, #16
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r3, r1, #24
+; CHECK-T1-NEXT: lsls r1, r0, #24
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: adds r0, r1, r3
+; CHECK-T1-NEXT: mov r3, r2
+; CHECK-T1-NEXT: bmi .LBB3_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: .LBB3_2:
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: bne .LBB3_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvs .LBB3_5
+; CHECK-T1-NEXT: b .LBB3_6
+; CHECK-T1-NEXT: .LBB3_4:
+; CHECK-T1-NEXT: ldr r2, .LCPI3_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvc .LBB3_6
+; CHECK-T1-NEXT: .LBB3_5:
+; CHECK-T1-NEXT: mov r0, r2
+; CHECK-T1-NEXT: .LBB3_6:
+; CHECK-T1-NEXT: asrs r0, r0, #24
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI3_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #24
+; CHECK-T2-NEXT: mov.w r3, #-2147483648
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #24
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp r1, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r2, #1
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r3, #-2147483648
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #24
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r3, r1
+; CHECK-T2-NEXT: asrs r0, r3, #24
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #24
+; CHECK-ARM-NEXT: mov r3, #-2147483648
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #24
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r1, #0
+; CHECK-ARM-NEXT: movwmi r2, #1
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: mvnne r3, #-2147483648
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #24
+; CHECK-ARM-NEXT: movvc r3, r1
+; CHECK-ARM-NEXT: asr r0, r3, #24
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r3, r1, #28
+; CHECK-T1-NEXT: lsls r1, r0, #28
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: adds r0, r1, r3
+; CHECK-T1-NEXT: mov r3, r2
+; CHECK-T1-NEXT: bmi .LBB4_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: .LBB4_2:
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: bne .LBB4_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvs .LBB4_5
+; CHECK-T1-NEXT: b .LBB4_6
+; CHECK-T1-NEXT: .LBB4_4:
+; CHECK-T1-NEXT: ldr r2, .LCPI4_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bvc .LBB4_6
+; CHECK-T1-NEXT: .LBB4_5:
+; CHECK-T1-NEXT: mov r0, r2
+; CHECK-T1-NEXT: .LBB4_6:
+; CHECK-T1-NEXT: asrs r0, r0, #28
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI4_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #28
+; CHECK-T2-NEXT: mov.w r3, #-2147483648
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #28
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp r1, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r2, #1
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r3, #-2147483648
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #28
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r3, r1
+; CHECK-T2-NEXT: asrs r0, r3, #28
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #28
+; CHECK-ARM-NEXT: mov r3, #-2147483648
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #28
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: cmp r1, #0
+; CHECK-ARM-NEXT: movwmi r2, #1
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: mvnne r3, #-2147483648
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #28
+; CHECK-ARM-NEXT: movvc r3, r1
+; CHECK-ARM-NEXT: asr r0, r3, #28
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/ARM/ssub_sat.ll b/test/CodeGen/ARM/ssub_sat.ll
index b31dc0f..c6305ce 100644
--- a/test/CodeGen/ARM/ssub_sat.ll
+++ b/test/CodeGen/ARM/ssub_sat.ll
@@ -209,7 +209,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, lr}
@@ -280,7 +280,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, lr}
@@ -351,7 +351,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, lr}
diff --git a/test/CodeGen/ARM/ssub_sat_plus.ll b/test/CodeGen/ARM/ssub_sat_plus.ll
new file mode 100644
index 0000000..67c6553
--- /dev/null
+++ b/test/CodeGen/ARM/ssub_sat_plus.ll
@@ -0,0 +1,445 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: mov r3, r0
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: mov r4, r2
+; CHECK-T1-NEXT: bmi .LBB0_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: .LBB0_2:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB0_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r3, r1
+; CHECK-T1-NEXT: bvs .LBB0_5
+; CHECK-T1-NEXT: b .LBB0_6
+; CHECK-T1-NEXT: .LBB0_4:
+; CHECK-T1-NEXT: ldr r2, .LCPI0_0
+; CHECK-T1-NEXT: cmp r3, r1
+; CHECK-T1-NEXT: bvc .LBB0_6
+; CHECK-T1-NEXT: .LBB0_5:
+; CHECK-T1-NEXT: mov r0, r2
+; CHECK-T1-NEXT: .LBB0_6:
+; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI0_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: .save {r7, lr}
+; CHECK-T2-NEXT: push {r7, lr}
+; CHECK-T2-NEXT: mls r12, r1, r2, r0
+; CHECK-T2-NEXT: mov.w lr, #0
+; CHECK-T2-NEXT: mov.w r3, #-2147483648
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: cmp.w r12, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi.w lr, #1
+; CHECK-T2-NEXT: cmp.w lr, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r3, #-2147483648
+; CHECK-T2-NEXT: cmp r0, r1
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r3, r12
+; CHECK-T2-NEXT: mov r0, r3
+; CHECK-T2-NEXT: pop {r7, pc}
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mls r3, r1, r2, r0
+; CHECK-ARM-NEXT: mul r12, r1, r2
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: movwmi r2, #1
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: mvnne r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r0, r12
+; CHECK-ARM-NEXT: movvc r1, r3
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT: .pad #4
+; CHECK-T1-NEXT: sub sp, #4
+; CHECK-T1-NEXT: ldr r5, [sp, #28]
+; CHECK-T1-NEXT: movs r2, #1
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: cmp r5, #0
+; CHECK-T1-NEXT: mov r3, r2
+; CHECK-T1-NEXT: bge .LBB1_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: mov r3, r4
+; CHECK-T1-NEXT: .LBB1_2:
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: mov r6, r2
+; CHECK-T1-NEXT: bge .LBB1_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: mov r6, r4
+; CHECK-T1-NEXT: .LBB1_4:
+; CHECK-T1-NEXT: subs r3, r6, r3
+; CHECK-T1-NEXT: subs r7, r3, #1
+; CHECK-T1-NEXT: sbcs r3, r7
+; CHECK-T1-NEXT: ldr r7, [sp, #24]
+; CHECK-T1-NEXT: subs r0, r0, r7
+; CHECK-T1-NEXT: sbcs r1, r5
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: mov r5, r2
+; CHECK-T1-NEXT: bge .LBB1_6
+; CHECK-T1-NEXT: @ %bb.5:
+; CHECK-T1-NEXT: mov r5, r4
+; CHECK-T1-NEXT: .LBB1_6:
+; CHECK-T1-NEXT: subs r4, r6, r5
+; CHECK-T1-NEXT: subs r5, r4, #1
+; CHECK-T1-NEXT: sbcs r4, r5
+; CHECK-T1-NEXT: ands r3, r4
+; CHECK-T1-NEXT: beq .LBB1_8
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: asrs r0, r1, #31
+; CHECK-T1-NEXT: .LBB1_8:
+; CHECK-T1-NEXT: cmp r1, #0
+; CHECK-T1-NEXT: bmi .LBB1_10
+; CHECK-T1-NEXT: @ %bb.9:
+; CHECK-T1-NEXT: lsls r2, r2, #31
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: beq .LBB1_11
+; CHECK-T1-NEXT: b .LBB1_12
+; CHECK-T1-NEXT: .LBB1_10:
+; CHECK-T1-NEXT: ldr r2, .LCPI1_0
+; CHECK-T1-NEXT: cmp r3, #0
+; CHECK-T1-NEXT: bne .LBB1_12
+; CHECK-T1-NEXT: .LBB1_11:
+; CHECK-T1-NEXT: mov r2, r1
+; CHECK-T1-NEXT: .LBB1_12:
+; CHECK-T1-NEXT: mov r1, r2
+; CHECK-T1-NEXT: add sp, #4
+; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.13:
+; CHECK-T1-NEXT: .LCPI1_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: .save {r4, lr}
+; CHECK-T2-NEXT: push {r4, lr}
+; CHECK-T2-NEXT: ldr.w r12, [sp, #12]
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: ldr r4, [sp, #8]
+; CHECK-T2-NEXT: cmp.w r12, #-1
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r2, #1
+; CHECK-T2-NEXT: cmp.w r1, #-1
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r3, #1
+; CHECK-T2-NEXT: subs r2, r3, r2
+; CHECK-T2-NEXT: mov.w lr, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r2, #1
+; CHECK-T2-NEXT: subs r0, r0, r4
+; CHECK-T2-NEXT: sbc.w r4, r1, r12
+; CHECK-T2-NEXT: cmp.w r4, #-1
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt.w lr, #1
+; CHECK-T2-NEXT: subs.w r1, r3, lr
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r1, #1
+; CHECK-T2-NEXT: ands r2, r1
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: asrne r0, r4, #31
+; CHECK-T2-NEXT: cmp r4, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: mvnmi r1, #-2147483648
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it eq
+; CHECK-T2-NEXT: moveq r1, r4
+; CHECK-T2-NEXT: pop {r4, pc}
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: .save {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: push {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: ldr lr, [sp, #20]
+; CHECK-ARM-NEXT: cmn r1, #1
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: mov r4, #0
+; CHECK-ARM-NEXT: movwgt r3, #1
+; CHECK-ARM-NEXT: cmn lr, #1
+; CHECK-ARM-NEXT: movwgt r4, #1
+; CHECK-ARM-NEXT: ldr r12, [sp, #16]
+; CHECK-ARM-NEXT: subs r4, r3, r4
+; CHECK-ARM-NEXT: mov r5, #0
+; CHECK-ARM-NEXT: movwne r4, #1
+; CHECK-ARM-NEXT: subs r0, r0, r12
+; CHECK-ARM-NEXT: sbc r2, r1, lr
+; CHECK-ARM-NEXT: cmn r2, #1
+; CHECK-ARM-NEXT: movwgt r5, #1
+; CHECK-ARM-NEXT: subs r1, r3, r5
+; CHECK-ARM-NEXT: movwne r1, #1
+; CHECK-ARM-NEXT: ands r3, r4, r1
+; CHECK-ARM-NEXT: asrne r0, r2, #31
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: moveq r1, r2
+; CHECK-ARM-NEXT: pop {r4, r5, r11, pc}
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: lsls r2, r0, #16
+; CHECK-T1-NEXT: movs r3, #1
+; CHECK-T1-NEXT: subs r0, r2, r1
+; CHECK-T1-NEXT: mov r4, r3
+; CHECK-T1-NEXT: bmi .LBB2_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: .LBB2_2:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB2_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r3, r3, #31
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvs .LBB2_5
+; CHECK-T1-NEXT: b .LBB2_6
+; CHECK-T1-NEXT: .LBB2_4:
+; CHECK-T1-NEXT: ldr r3, .LCPI2_0
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvc .LBB2_6
+; CHECK-T1-NEXT: .LBB2_5:
+; CHECK-T1-NEXT: mov r0, r3
+; CHECK-T1-NEXT: .LBB2_6:
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI2_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mul r12, r1, r2
+; CHECK-T2-NEXT: lsls r0, r0, #16
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #16
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r3, #1
+; CHECK-T2-NEXT: cmp r3, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r1, #-2147483648
+; CHECK-T2-NEXT: cmp.w r0, r12, lsl #16
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r1, r2
+; CHECK-T2-NEXT: asrs r0, r1, #16
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r12, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #16
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #16
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: movwmi r3, #1
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: mvnne r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r0, r12, lsl #16
+; CHECK-ARM-NEXT: movvc r1, r2
+; CHECK-ARM-NEXT: asr r0, r1, #16
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #24
+; CHECK-T1-NEXT: lsls r2, r0, #24
+; CHECK-T1-NEXT: movs r3, #1
+; CHECK-T1-NEXT: subs r0, r2, r1
+; CHECK-T1-NEXT: mov r4, r3
+; CHECK-T1-NEXT: bmi .LBB3_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: .LBB3_2:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB3_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r3, r3, #31
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvs .LBB3_5
+; CHECK-T1-NEXT: b .LBB3_6
+; CHECK-T1-NEXT: .LBB3_4:
+; CHECK-T1-NEXT: ldr r3, .LCPI3_0
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvc .LBB3_6
+; CHECK-T1-NEXT: .LBB3_5:
+; CHECK-T1-NEXT: mov r0, r3
+; CHECK-T1-NEXT: .LBB3_6:
+; CHECK-T1-NEXT: asrs r0, r0, #24
+; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI3_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mul r12, r1, r2
+; CHECK-T2-NEXT: lsls r0, r0, #24
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #24
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r3, #1
+; CHECK-T2-NEXT: cmp r3, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r1, #-2147483648
+; CHECK-T2-NEXT: cmp.w r0, r12, lsl #24
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r1, r2
+; CHECK-T2-NEXT: asrs r0, r1, #24
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r12, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #24
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #24
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: movwmi r3, #1
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: mvnne r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r0, r12, lsl #24
+; CHECK-ARM-NEXT: movvc r1, r2
+; CHECK-ARM-NEXT: asr r0, r1, #24
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #28
+; CHECK-T1-NEXT: lsls r2, r0, #28
+; CHECK-T1-NEXT: movs r3, #1
+; CHECK-T1-NEXT: subs r0, r2, r1
+; CHECK-T1-NEXT: mov r4, r3
+; CHECK-T1-NEXT: bmi .LBB4_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: .LBB4_2:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB4_4
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: lsls r3, r3, #31
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvs .LBB4_5
+; CHECK-T1-NEXT: b .LBB4_6
+; CHECK-T1-NEXT: .LBB4_4:
+; CHECK-T1-NEXT: ldr r3, .LCPI4_0
+; CHECK-T1-NEXT: cmp r2, r1
+; CHECK-T1-NEXT: bvc .LBB4_6
+; CHECK-T1-NEXT: .LBB4_5:
+; CHECK-T1-NEXT: mov r0, r3
+; CHECK-T1-NEXT: .LBB4_6:
+; CHECK-T1-NEXT: asrs r0, r0, #28
+; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.7:
+; CHECK-T1-NEXT: .LCPI4_0:
+; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mul r12, r1, r2
+; CHECK-T2-NEXT: lsls r0, r0, #28
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #28
+; CHECK-T2-NEXT: cmp r2, #0
+; CHECK-T2-NEXT: it mi
+; CHECK-T2-NEXT: movmi r3, #1
+; CHECK-T2-NEXT: cmp r3, #0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: mvnne r1, #-2147483648
+; CHECK-T2-NEXT: cmp.w r0, r12, lsl #28
+; CHECK-T2-NEXT: it vc
+; CHECK-T2-NEXT: movvc r1, r2
+; CHECK-T2-NEXT: asrs r0, r1, #28
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r12, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #28
+; CHECK-ARM-NEXT: mov r3, #0
+; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #28
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: movwmi r3, #1
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: mvnne r1, #-2147483648
+; CHECK-ARM-NEXT: cmp r0, r12, lsl #28
+; CHECK-ARM-NEXT: movvc r1, r2
+; CHECK-ARM-NEXT: asr r0, r1, #28
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/ARM/uadd_sat.ll b/test/CodeGen/ARM/uadd_sat.ll
index 2843f85..3de6595 100644
--- a/test/CodeGen/ARM/uadd_sat.ll
+++ b/test/CodeGen/ARM/uadd_sat.ll
@@ -90,7 +90,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #16
@@ -126,7 +126,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #24
@@ -162,7 +162,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #28
diff --git a/test/CodeGen/ARM/uadd_sat_plus.ll b/test/CodeGen/ARM/uadd_sat_plus.ll
new file mode 100644
index 0000000..64f7c0d
--- /dev/null
+++ b/test/CodeGen/ARM/uadd_sat_plus.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.uadd.sat.i4(i4, i4)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: blo .LBB0_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r0, r0
+; CHECK-T1-NEXT: .LBB0_2:
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: adds r0, r0, r1
+; CHECK-T2-NEXT: it hs
+; CHECK-T2-NEXT: movhs.w r0, #-1
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mul r1, r1, r2
+; CHECK-ARM-NEXT: adds r0, r0, r1
+; CHECK-ARM-NEXT: mvnhs r0, #0
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
+; CHECK-T1-NEXT: push {r4, r5, r7, lr}
+; CHECK-T1-NEXT: movs r5, #0
+; CHECK-T1-NEXT: ldr r2, [sp, #20]
+; CHECK-T1-NEXT: ldr r3, [sp, #16]
+; CHECK-T1-NEXT: adds r3, r0, r3
+; CHECK-T1-NEXT: adcs r2, r1
+; CHECK-T1-NEXT: mov r4, r5
+; CHECK-T1-NEXT: adcs r4, r5
+; CHECK-T1-NEXT: mvns r1, r5
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: beq .LBB1_3
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: beq .LBB1_4
+; CHECK-T1-NEXT: .LBB1_2:
+; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
+; CHECK-T1-NEXT: .LBB1_3:
+; CHECK-T1-NEXT: mov r0, r3
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB1_2
+; CHECK-T1-NEXT: .LBB1_4:
+; CHECK-T1-NEXT: mov r1, r2
+; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: ldrd r2, r3, [sp]
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: adds r0, r0, r2
+; CHECK-T2-NEXT: adcs r1, r3
+; CHECK-T2-NEXT: adcs r2, r12, #0
+; CHECK-T2-NEXT: itt ne
+; CHECK-T2-NEXT: movne.w r0, #-1
+; CHECK-T2-NEXT: movne.w r1, #-1
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: ldr r2, [sp]
+; CHECK-ARM-NEXT: mov r12, #0
+; CHECK-ARM-NEXT: ldr r3, [sp, #4]
+; CHECK-ARM-NEXT: adds r0, r0, r2
+; CHECK-ARM-NEXT: adcs r1, r1, r3
+; CHECK-ARM-NEXT: adcs r2, r12, #0
+; CHECK-ARM-NEXT: mvnne r0, #0
+; CHECK-ARM-NEXT: mvnne r1, #0
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: blo .LBB2_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r0, r0
+; CHECK-T1-NEXT: .LBB2_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #16
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #16
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #16
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #16
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo.w r1, #-1
+; CHECK-T2-NEXT: lsrs r0, r1, #16
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mul r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #16
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #16
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #16
+; CHECK-ARM-NEXT: mvnlo r1, #0
+; CHECK-ARM-NEXT: lsr r0, r1, #16
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #24
+; CHECK-T1-NEXT: lsls r0, r0, #24
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: blo .LBB3_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r0, r0
+; CHECK-T1-NEXT: .LBB3_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #24
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #24
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #24
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #24
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo.w r1, #-1
+; CHECK-T2-NEXT: lsrs r0, r1, #24
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #24
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #24
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #24
+; CHECK-ARM-NEXT: mvnlo r1, #0
+; CHECK-ARM-NEXT: lsr r0, r1, #24
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #28
+; CHECK-T1-NEXT: lsls r0, r0, #28
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: blo .LBB4_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r0, r0
+; CHECK-T1-NEXT: .LBB4_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #28
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r2, r0, #28
+; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #28
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #28
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo.w r1, #-1
+; CHECK-T2-NEXT: lsrs r0, r1, #28
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r2, r0, #28
+; CHECK-ARM-NEXT: add r1, r2, r1, lsl #28
+; CHECK-ARM-NEXT: cmp r1, r0, lsl #28
+; CHECK-ARM-NEXT: mvnlo r1, #0
+; CHECK-ARM-NEXT: lsr r0, r1, #28
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/ARM/usub_sat.ll b/test/CodeGen/ARM/usub_sat.ll
index 5587cef..c080b02 100644
--- a/test/CodeGen/ARM/usub_sat.ll
+++ b/test/CodeGen/ARM/usub_sat.ll
@@ -90,7 +90,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #16
@@ -125,7 +125,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #24
@@ -160,7 +160,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: lsls r1, r1, #28
diff --git a/test/CodeGen/ARM/usub_sat_plus.ll b/test/CodeGen/ARM/usub_sat_plus.ll
new file mode 100644
index 0000000..dc1e6e5
--- /dev/null
+++ b/test/CodeGen/ARM/usub_sat_plus.ll
@@ -0,0 +1,218 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.usub.sat.i4(i4, i4)
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare i16 @llvm.usub.sat.i16(i16, i16)
+declare i32 @llvm.usub.sat.i32(i32, i32)
+declare i64 @llvm.usub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: bhs .LBB0_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: .LBB0_2:
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r0, #0
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mul r1, r1, r2
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movlo r0, #0
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: mov r2, r1
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: ldr r4, [sp, #12]
+; CHECK-T1-NEXT: ldr r3, [sp, #8]
+; CHECK-T1-NEXT: subs r3, r0, r3
+; CHECK-T1-NEXT: sbcs r2, r4
+; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: movs r4, #1
+; CHECK-T1-NEXT: subs r4, r4, r0
+; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: beq .LBB1_3
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: beq .LBB1_4
+; CHECK-T1-NEXT: .LBB1_2:
+; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T1-NEXT: .LBB1_3:
+; CHECK-T1-NEXT: mov r0, r3
+; CHECK-T1-NEXT: cmp r4, #0
+; CHECK-T1-NEXT: bne .LBB1_2
+; CHECK-T1-NEXT: .LBB1_4:
+; CHECK-T1-NEXT: mov r1, r2
+; CHECK-T1-NEXT: pop {r4, pc}
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: ldrd r2, r3, [sp]
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: subs r0, r0, r2
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: adc r2, r12, #0
+; CHECK-T2-NEXT: rsbs.w r2, r2, #1
+; CHECK-T2-NEXT: itt ne
+; CHECK-T2-NEXT: movne r0, #0
+; CHECK-T2-NEXT: movne r1, #0
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: ldr r2, [sp]
+; CHECK-ARM-NEXT: mov r12, #0
+; CHECK-ARM-NEXT: ldr r3, [sp, #4]
+; CHECK-ARM-NEXT: subs r0, r0, r2
+; CHECK-ARM-NEXT: sbcs r1, r1, r3
+; CHECK-ARM-NEXT: adc r2, r12, #0
+; CHECK-ARM-NEXT: rsbs r2, r2, #1
+; CHECK-ARM-NEXT: movwne r0, #0
+; CHECK-ARM-NEXT: movwne r1, #0
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: bhs .LBB2_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: .LBB2_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #16
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r0, r0, #16
+; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #16
+; CHECK-T2-NEXT: cmp.w r0, r1, lsl #16
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #0
+; CHECK-T2-NEXT: lsrs r0, r2, #16
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: mul r1, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #16
+; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #16
+; CHECK-ARM-NEXT: cmp r0, r1, lsl #16
+; CHECK-ARM-NEXT: movlo r2, #0
+; CHECK-ARM-NEXT: lsr r0, r2, #16
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #24
+; CHECK-T1-NEXT: lsls r0, r0, #24
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: bhs .LBB3_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: .LBB3_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #24
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r0, r0, #24
+; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #24
+; CHECK-T2-NEXT: cmp.w r0, r1, lsl #24
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #0
+; CHECK-T2-NEXT: lsrs r0, r2, #24
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #24
+; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #24
+; CHECK-ARM-NEXT: cmp r0, r1, lsl #24
+; CHECK-ARM-NEXT: movlo r2, #0
+; CHECK-ARM-NEXT: lsr r0, r2, #24
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: muls r1, r2, r1
+; CHECK-T1-NEXT: lsls r1, r1, #28
+; CHECK-T1-NEXT: lsls r0, r0, #28
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: bhs .LBB4_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: .LBB4_2:
+; CHECK-T1-NEXT: lsrs r0, r0, #28
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: muls r1, r2, r1
+; CHECK-T2-NEXT: lsls r0, r0, #28
+; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #28
+; CHECK-T2-NEXT: cmp.w r0, r1, lsl #28
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #0
+; CHECK-T2-NEXT: lsrs r0, r2, #28
+; CHECK-T2-NEXT: bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: smulbb r1, r1, r2
+; CHECK-ARM-NEXT: lsl r0, r0, #28
+; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #28
+; CHECK-ARM-NEXT: cmp r0, r1, lsl #28
+; CHECK-ARM-NEXT: movlo r2, #0
+; CHECK-ARM-NEXT: lsr r0, r2, #28
+; CHECK-ARM-NEXT: bx lr
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/X86/sadd_sat.ll b/test/CodeGen/X86/sadd_sat.ll
index 6d853d7..485e547 100644
--- a/test/CodeGen/X86/sadd_sat.ll
+++ b/test/CodeGen/X86/sadd_sat.ll
@@ -91,7 +91,7 @@
ret i64 %tmp;
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; X86-LABEL: func16:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
@@ -123,7 +123,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -155,39 +155,39 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; X86-LABEL: func3:
; X86: # %bb.0:
-; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NEXT: shlb $4, %dl
-; X86-NEXT: shlb $4, %al
-; X86-NEXT: xorl %ecx, %ecx
-; X86-NEXT: movb %al, %ah
-; X86-NEXT: addb %dl, %ah
-; X86-NEXT: setns %cl
-; X86-NEXT: addl $127, %ecx
-; X86-NEXT: addb %dl, %al
-; X86-NEXT: movzbl %al, %eax
-; X86-NEXT: cmovol %ecx, %eax
-; X86-NEXT: sarb $4, %al
-; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: shlb $4, %cl
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: movb %cl, %ch
+; X86-NEXT: addb %dl, %ch
+; X86-NEXT: setns %al
+; X86-NEXT: addl $127, %eax
+; X86-NEXT: addb %dl, %cl
+; X86-NEXT: movzbl %cl, %ecx
+; X86-NEXT: cmovol %eax, %ecx
+; X86-NEXT: sarb $4, %cl
+; X86-NEXT: movsbl %cl, %eax
; X86-NEXT: retl
;
; X64-LABEL: func3:
; X64: # %bb.0:
; X64-NEXT: shlb $4, %sil
; X64-NEXT: shlb $4, %dil
-; X64-NEXT: xorl %ecx, %ecx
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: addb %sil, %al
-; X64-NEXT: setns %cl
-; X64-NEXT: addl $127, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: addb %sil, %cl
+; X64-NEXT: setns %al
+; X64-NEXT: addl $127, %eax
; X64-NEXT: addb %sil, %dil
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: cmovol %ecx, %eax
-; X64-NEXT: sarb $4, %al
-; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cmovol %eax, %ecx
+; X64-NEXT: sarb $4, %cl
+; X64-NEXT: movsbl %cl, %eax
; X64-NEXT: retq
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/test/CodeGen/X86/sadd_sat_plus.ll b/test/CodeGen/X86/sadd_sat_plus.ll
new file mode 100644
index 0000000..76cc161
--- /dev/null
+++ b/test/CodeGen/X86/sadd_sat_plus.ll
@@ -0,0 +1,210 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; X86-LABEL: func32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: imull {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: addl %edx, %esi
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+;
+; X64-LABEL: func32:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: addl %esi, %ecx
+; X64-NEXT: setns %al
+; X64-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: addl %edi, %esi
+; X64-NEXT: cmovnol %esi, %eax
+; X64-NEXT: retq
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; X86-LABEL: func64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: addl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: adcl %esi, %ebp
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: sarl $31, %eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %ebp, %ebp
+; X86-NEXT: setns %cl
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF
+; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: setns %bl
+; X86-NEXT: cmpb %cl, %bl
+; X86-NEXT: setne %cl
+; X86-NEXT: testl %esi, %esi
+; X86-NEXT: setns %ch
+; X86-NEXT: cmpb %ch, %bl
+; X86-NEXT: sete %ch
+; X86-NEXT: testb %cl, %ch
+; X86-NEXT: cmovel %ebp, %edx
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl
+;
+; X64-LABEL: func64:
+; X64: # %bb.0:
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: addq %rdx, %rax
+; X64-NEXT: setns %cl
+; X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: addq %rdx, %rdi
+; X64-NEXT: cmovnoq %rdi, %rax
+; X64-NEXT: retq
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; X86-LABEL: func16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: imulw {{[0-9]+}}(%esp), %ax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: addw %dx, %si
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $32767, %ecx # imm = 0x7FFF
+; X86-NEXT: addw %dx, %ax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+;
+; X64-LABEL: func16:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: addw %si, %cx
+; X64-NEXT: setns %al
+; X64-NEXT: addl $32767, %eax # imm = 0x7FFF
+; X64-NEXT: addw %si, %di
+; X64-NEXT: cmovnol %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; X86-LABEL: func8:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: movb %al, %ah
+; X86-NEXT: addb %dl, %ah
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $127, %ecx
+; X86-NEXT: addb %dl, %al
+; X86-NEXT: movzbl %al, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: movl %edi, %edx
+; X64-NEXT: addb %al, %dl
+; X64-NEXT: setns %cl
+; X64-NEXT: addl $127, %ecx
+; X64-NEXT: addb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovol %ecx, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; X86-LABEL: func4:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: shlb $4, %al
+; X86-NEXT: shlb $4, %dl
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: movb %dl, %ah
+; X86-NEXT: addb %al, %ah
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $127, %ecx
+; X86-NEXT: addb %al, %dl
+; X86-NEXT: movzbl %dl, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: sarb $4, %al
+; X86-NEXT: movsbl %al, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func4:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: shlb $4, %al
+; X64-NEXT: shlb $4, %dil
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: movl %edi, %edx
+; X64-NEXT: addb %al, %dl
+; X64-NEXT: setns %cl
+; X64-NEXT: addl $127, %ecx
+; X64-NEXT: addb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovol %ecx, %eax
+; X64-NEXT: sarb $4, %al
+; X64-NEXT: movsbl %al, %eax
+; X64-NEXT: retq
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/X86/ssub_sat.ll b/test/CodeGen/X86/ssub_sat.ll
index 51ca6d8..a92905a 100644
--- a/test/CodeGen/X86/ssub_sat.ll
+++ b/test/CodeGen/X86/ssub_sat.ll
@@ -86,7 +86,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; X86-LABEL: func16:
; X86: # %bb.0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -114,7 +114,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -144,37 +144,37 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; X86-LABEL: func3:
; X86: # %bb.0:
-; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NEXT: shlb $4, %dl
-; X86-NEXT: shlb $4, %al
-; X86-NEXT: xorl %ecx, %ecx
-; X86-NEXT: cmpb %dl, %al
-; X86-NEXT: setns %cl
-; X86-NEXT: addl $127, %ecx
-; X86-NEXT: subb %dl, %al
-; X86-NEXT: movzbl %al, %eax
-; X86-NEXT: cmovol %ecx, %eax
-; X86-NEXT: sarb $4, %al
-; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: shlb $4, %cl
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpb %dl, %cl
+; X86-NEXT: setns %al
+; X86-NEXT: addl $127, %eax
+; X86-NEXT: subb %dl, %cl
+; X86-NEXT: movzbl %cl, %ecx
+; X86-NEXT: cmovol %eax, %ecx
+; X86-NEXT: sarb $4, %cl
+; X86-NEXT: movsbl %cl, %eax
; X86-NEXT: retl
;
; X64-LABEL: func3:
; X64: # %bb.0:
; X64-NEXT: shlb $4, %sil
; X64-NEXT: shlb $4, %dil
-; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: xorl %eax, %eax
; X64-NEXT: cmpb %sil, %dil
-; X64-NEXT: setns %cl
-; X64-NEXT: addl $127, %ecx
+; X64-NEXT: setns %al
+; X64-NEXT: addl $127, %eax
; X64-NEXT: subb %sil, %dil
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: cmovol %ecx, %eax
-; X64-NEXT: sarb $4, %al
-; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cmovol %eax, %ecx
+; X64-NEXT: sarb $4, %cl
+; X64-NEXT: movsbl %cl, %eax
; X64-NEXT: retq
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y)
ret i4 %tmp
diff --git a/test/CodeGen/X86/ssub_sat_plus.ll b/test/CodeGen/X86/ssub_sat_plus.ll
new file mode 100644
index 0000000..ed0718e
--- /dev/null
+++ b/test/CodeGen/X86/ssub_sat_plus.ll
@@ -0,0 +1,197 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; X86-LABEL: func32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %edx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X86-NEXT: subl %edx, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func32:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: setns %al
+; X64-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: subl %esi, %edi
+; X64-NEXT: cmovnol %edi, %eax
+; X64-NEXT: retq
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; X86-LABEL: func64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: sbbl %esi, %ebp
+; X86-NEXT: movl %ebp, %eax
+; X86-NEXT: sarl $31, %eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %ebp, %ebp
+; X86-NEXT: setns %cl
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF
+; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: setns %bl
+; X86-NEXT: cmpb %cl, %bl
+; X86-NEXT: setne %cl
+; X86-NEXT: testl %esi, %esi
+; X86-NEXT: setns %ch
+; X86-NEXT: cmpb %ch, %bl
+; X86-NEXT: setne %ch
+; X86-NEXT: testb %cl, %ch
+; X86-NEXT: cmovel %ebp, %edx
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl
+;
+; X64-LABEL: func64:
+; X64: # %bb.0:
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: cmpq %rdx, %rdi
+; X64-NEXT: setns %cl
+; X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: subq %rdx, %rdi
+; X64-NEXT: cmovnoq %rdi, %rax
+; X64-NEXT: retq
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; X86-LABEL: func16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: imulw {{[0-9]+}}(%esp), %dx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $32767, %ecx # imm = 0x7FFF
+; X86-NEXT: subw %dx, %ax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func16:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpw %si, %di
+; X64-NEXT: setns %al
+; X64-NEXT: addl $32767, %eax # imm = 0x7FFF
+; X64-NEXT: subw %si, %di
+; X64-NEXT: cmovnol %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; X86-LABEL: func8:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpb %al, %dl
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $127, %ecx
+; X86-NEXT: subb %al, %dl
+; X86-NEXT: movzbl %dl, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: setns %cl
+; X64-NEXT: addl $127, %ecx
+; X64-NEXT: subb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovol %ecx, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; X86-LABEL: func4:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: shlb $4, %al
+; X86-NEXT: shlb $4, %dl
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpb %al, %dl
+; X86-NEXT: setns %cl
+; X86-NEXT: addl $127, %ecx
+; X86-NEXT: subb %al, %dl
+; X86-NEXT: movzbl %dl, %eax
+; X86-NEXT: cmovol %ecx, %eax
+; X86-NEXT: sarb $4, %al
+; X86-NEXT: movsbl %al, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func4:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: shlb $4, %al
+; X64-NEXT: shlb $4, %dil
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: setns %cl
+; X64-NEXT: addl $127, %ecx
+; X64-NEXT: subb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovol %ecx, %eax
+; X64-NEXT: sarb $4, %al
+; X64-NEXT: movsbl %al, %eax
+; X64-NEXT: retq
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/X86/uadd_sat.ll b/test/CodeGen/X86/uadd_sat.ll
index 203d039..7124e45 100644
--- a/test/CodeGen/X86/uadd_sat.ll
+++ b/test/CodeGen/X86/uadd_sat.ll
@@ -50,7 +50,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; X86-LABEL: func16:
; X86: # %bb.0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
@@ -71,7 +71,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -94,7 +94,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; X86-LABEL: func3:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -102,11 +102,11 @@
; X86-NEXT: shlb $4, %cl
; X86-NEXT: shlb $4, %al
; X86-NEXT: addb %cl, %al
-; X86-NEXT: movzbl %al, %ecx
-; X86-NEXT: movl $255, %eax
-; X86-NEXT: cmovael %ecx, %eax
-; X86-NEXT: shrb $4, %al
-; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: movzbl %al, %eax
+; X86-NEXT: movl $255, %ecx
+; X86-NEXT: cmovael %eax, %ecx
+; X86-NEXT: shrb $4, %cl
+; X86-NEXT: movzbl %cl, %eax
; X86-NEXT: retl
;
; X64-LABEL: func3:
@@ -114,11 +114,11 @@
; X64-NEXT: shlb $4, %sil
; X64-NEXT: shlb $4, %dil
; X64-NEXT: addb %sil, %dil
-; X64-NEXT: movzbl %dil, %ecx
-; X64-NEXT: movl $255, %eax
-; X64-NEXT: cmovael %ecx, %eax
-; X64-NEXT: shrb $4, %al
-; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: movl $255, %ecx
+; X64-NEXT: cmovael %eax, %ecx
+; X64-NEXT: shrb $4, %cl
+; X64-NEXT: movzbl %cl, %eax
; X64-NEXT: retq
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y)
ret i4 %tmp
diff --git a/test/CodeGen/X86/uadd_sat_plus.ll b/test/CodeGen/X86/uadd_sat_plus.ll
new file mode 100644
index 0000000..428e293
--- /dev/null
+++ b/test/CodeGen/X86/uadd_sat_plus.ll
@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
+
+declare i4 @llvm.uadd.sat.i4(i4, i4)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; X86-LABEL: func32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: addl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl $-1, %eax
+; X86-NEXT: cmovael %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func32:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: addl %edi, %esi
+; X64-NEXT: movl $-1, %eax
+; X64-NEXT: cmovael %esi, %eax
+; X64-NEXT: retq
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; X86-LABEL: func64:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl $-1, %ecx
+; X86-NEXT: cmovbl %ecx, %edx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func64:
+; X64: # %bb.0:
+; X64-NEXT: addq %rdx, %rdi
+; X64-NEXT: movq $-1, %rax
+; X64-NEXT: cmovaeq %rdi, %rax
+; X64-NEXT: retq
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; X86-LABEL: func16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imulw {{[0-9]+}}(%esp), %cx
+; X86-NEXT: addw {{[0-9]+}}(%esp), %cx
+; X86-NEXT: movl $65535, %eax # imm = 0xFFFF
+; X86-NEXT: cmovael %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func16:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: addw %di, %si
+; X64-NEXT: movl $65535, %eax # imm = 0xFFFF
+; X64-NEXT: cmovael %esi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; X86-LABEL: func8:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: addb {{[0-9]+}}(%esp), %al
+; X86-NEXT: movzbl %al, %ecx
+; X86-NEXT: movl $255, %eax
+; X86-NEXT: cmovael %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: addb %dil, %al
+; X64-NEXT: movzbl %al, %ecx
+; X64-NEXT: movl $255, %eax
+; X64-NEXT: cmovael %ecx, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; X86-LABEL: func4:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: shlb $4, %al
+; X86-NEXT: shlb $4, %cl
+; X86-NEXT: addb %al, %cl
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: movl $255, %ecx
+; X86-NEXT: cmovael %eax, %ecx
+; X86-NEXT: shrb $4, %cl
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func4:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: shlb $4, %al
+; X64-NEXT: shlb $4, %dil
+; X64-NEXT: addb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: movl $255, %ecx
+; X64-NEXT: cmovael %eax, %ecx
+; X64-NEXT: shrb $4, %cl
+; X64-NEXT: movzbl %cl, %eax
+; X64-NEXT: retq
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/test/CodeGen/X86/usub_sat.ll b/test/CodeGen/X86/usub_sat.ll
index 55cb6e8..a7de6b5 100644
--- a/test/CodeGen/X86/usub_sat.ll
+++ b/test/CodeGen/X86/usub_sat.ll
@@ -50,7 +50,7 @@
ret i64 %tmp
}
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; X86-LABEL: func16:
; X86: # %bb.0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -71,7 +71,7 @@
ret i16 %tmp
}
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -94,7 +94,7 @@
ret i8 %tmp
}
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; X86-LABEL: func3:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
@@ -106,19 +106,19 @@
; X86-NEXT: movzbl %al, %eax
; X86-NEXT: cmovbl %edx, %eax
; X86-NEXT: shrb $4, %al
-; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: movzbl %al, %eax
; X86-NEXT: retl
;
; X64-LABEL: func3:
; X64: # %bb.0:
; X64-NEXT: shlb $4, %sil
; X64-NEXT: shlb $4, %dil
-; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: xorl %eax, %eax
; X64-NEXT: subb %sil, %dil
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: cmovbl %ecx, %eax
-; X64-NEXT: shrb $4, %al
-; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: movzbl %dil, %ecx
+; X64-NEXT: cmovbl %eax, %ecx
+; X64-NEXT: shrb $4, %cl
+; X64-NEXT: movzbl %cl, %eax
; X64-NEXT: retq
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
ret i4 %tmp
diff --git a/test/CodeGen/X86/usub_sat_plus.ll b/test/CodeGen/X86/usub_sat_plus.ll
new file mode 100644
index 0000000..6a9e5a4
--- /dev/null
+++ b/test/CodeGen/X86/usub_sat_plus.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
+
+declare i4 @llvm.usub.sat.i4(i4, i4)
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare i16 @llvm.usub.sat.i16(i16, i16)
+declare i32 @llvm.usub.sat.i32(i32, i32)
+declare i64 @llvm.usub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; X86-LABEL: func32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: cmovbl %edx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func32:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: subl %esi, %edi
+; X64-NEXT: cmovael %edi, %eax
+; X64-NEXT: retq
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; X86-LABEL: func64:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: sbbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmovbl %ecx, %edx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func64:
+; X64: # %bb.0:
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: subq %rdx, %rdi
+; X64-NEXT: cmovaeq %rdi, %rax
+; X64-NEXT: retq
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; X86-LABEL: func16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imulw {{[0-9]+}}(%esp), %cx
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: subw %cx, %ax
+; X86-NEXT: cmovbl %edx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func16:
+; X64: # %bb.0:
+; X64-NEXT: imull %edx, %esi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: subw %si, %di
+; X64-NEXT: cmovael %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; X86-LABEL: func8:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: subb %al, %cl
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: cmovbl %edx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: subb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovbl %ecx, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; X86-LABEL: func4:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: shlb $4, %al
+; X86-NEXT: shlb $4, %cl
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: subb %al, %cl
+; X86-NEXT: movzbl %cl, %eax
+; X86-NEXT: cmovbl %edx, %eax
+; X86-NEXT: shrb $4, %al
+; X86-NEXT: movzbl %al, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: func4:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: mulb %dl
+; X64-NEXT: shlb $4, %al
+; X64-NEXT: shlb $4, %dil
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: subb %al, %dil
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: cmovbl %ecx, %eax
+; X64-NEXT: shrb $4, %al
+; X64-NEXT: movzbl %al, %eax
+; X64-NEXT: retq
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
