[X86] Add test cases for turning (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) when the AND could match to a movzx.
We already reorder when C1 >> C2 would allow a smaller immediate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358736 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll
index 782fe22..0100a8c 100644
--- a/test/CodeGen/X86/narrow-shl-cst.ll
+++ b/test/CodeGen/X86/narrow-shl-cst.ll
@@ -197,3 +197,62 @@
%shl = xor i64 %xor, 1095216660480
ret i64 %shl
}
+
+define i32 @test17(i32 %x) nounwind {
+; CHECK-LABEL: test17:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shll $10, %eax
+; CHECK-NEXT: andl $261120, %eax # imm = 0x3FC00
+; CHECK-NEXT: retq
+ %and = shl i32 %x, 10
+ %shl = and i32 %and, 261120
+ ret i32 %shl
+}
+
+define i64 @test18(i64 %x) nounwind {
+; CHECK-LABEL: test18:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shll $10, %eax
+; CHECK-NEXT: andl $261120, %eax # imm = 0x3FC00
+; CHECK-NEXT: retq
+ %and = shl i64 %x, 10
+ %shl = and i64 %and, 261120
+ ret i64 %shl
+}
+
+define i32 @test19(i32 %x) nounwind {
+; CHECK-LABEL: test19:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shll $10, %eax
+; CHECK-NEXT: andl $67107840, %eax # imm = 0x3FFFC00
+; CHECK-NEXT: retq
+ %and = shl i32 %x, 10
+ %shl = and i32 %and, 67107840
+ ret i32 %shl
+}
+
+define i64 @test20(i64 %x) nounwind {
+; CHECK-LABEL: test20:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shll $10, %eax
+; CHECK-NEXT: andl $67107840, %eax # imm = 0x3FFFC00
+; CHECK-NEXT: retq
+ %and = shl i64 %x, 10
+ %shl = and i64 %and, 67107840
+ ret i64 %shl
+}
+
+define i64 @test21(i64 %x) nounwind {
+; CHECK-LABEL: test21:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlq $10, %rax
+; CHECK-NEXT: retq
+ %and = shl i64 %x, 10
+ %shl = and i64 %and, 4398046510080
+ ret i64 %shl
+}
