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llvm
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llvm
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eec7ef7443ddbd32d9328160c31a628642198dc8
/
.
/
test
/
CodeGen
/
Hexagon
/
vect
/
vect-vsubw.ll
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; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vsubw
define
<
2
x
i32
>
@t_i2x32
(<
2
x
i32
>
%a
,
<
2
x
i32
>
%b
)
nounwind
{
entry
:
%0
=
sub
<
2
x
i32
>
%a
,
%b
ret
<
2
x
i32
>
%0
}