commit e6effacc17de2a9eb4b6609c1b7723a5c8a51034
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Feb 22 19:03:36 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Feb 22 19:03:36 2019 +0000
tree 5cbe09948b1006a896f2848484da30ec5056c683
parent fa8a50ce70eba71f10c1c7a6ff598d47227f8f51

AMDGPU: Use removeAllRegUnitsForPhysReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354686 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/SILowerControlFlow.cpp

diff --git a/lib/Target/AMDGPU/SILowerControlFlow.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 2004280..d8ee8e3 100644
--- a/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -239,7 +239,7 @@
   LIS->InsertMachineInstrInMaps(*SetExec);
   LIS->InsertMachineInstrInMaps(*NewBr);
 
-  LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC, TRI));
+  LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
   MI.eraseFromParent();
 
   // FIXME: Is there a better way of adjusting the liveness? It shouldn't be
@@ -323,7 +323,7 @@
     LIS->createAndComputeVirtRegInterval(SaveReg);
 
   // Let this be recomputed.
-  LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC, TRI));
+  LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
 }
 
 void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

diff --git a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index adf23a3..0819fde 100644
--- a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -374,8 +374,7 @@
         if (!MRI.reg_empty(Reg))
           LIS->createAndComputeVirtRegInterval(Reg);
       } else {
-        for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
-          LIS->removeRegUnit(*U);
+        LIS->removeAllRegUnitsForPhysReg(Reg);
       }
     }
   }