| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 |
| --- | |
| |
| |
| define void @and_i32() {entry: ret void} |
| define void @or_i32() {entry: ret void} |
| define void @xor_i32() {entry: ret void} |
| define void @shl(i32) {entry: ret void} |
| define void @ashr(i32) {entry: ret void} |
| define void @lshr(i32) {entry: ret void} |
| define void @shlv(i32, i32) {entry: ret void} |
| define void @ashrv(i32, i32) {entry: ret void} |
| define void @lshrv(i32, i32) {entry: ret void} |
| |
| ... |
| --- |
| name: and_i32 |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: and_i32 |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]] |
| ; MIPS32: $v0 = COPY [[AND]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_AND %1, %0 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: or_i32 |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: or_i32 |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]] |
| ; MIPS32: $v0 = COPY [[OR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_OR %1, %0 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: xor_i32 |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: xor_i32 |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]] |
| ; MIPS32: $v0 = COPY [[XOR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_XOR %1, %0 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: shl |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: shl |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 |
| ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]] |
| ; MIPS32: $v0 = COPY [[SHL]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = G_CONSTANT i32 1 |
| %2:_(s32) = G_SHL %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ashr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: ashr |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 |
| ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]] |
| ; MIPS32: $v0 = COPY [[ASHR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = G_CONSTANT i32 1 |
| %2:_(s32) = G_ASHR %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: lshr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: lshr |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 |
| ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]] |
| ; MIPS32: $v0 = COPY [[LSHR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = G_CONSTANT i32 1 |
| %2:_(s32) = G_LSHR %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: shlv |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: shlv |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]] |
| ; MIPS32: $v0 = COPY [[SHL]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_SHL %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ashrv |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ashrv |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]] |
| ; MIPS32: $v0 = COPY [[ASHR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_ASHR %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: lshrv |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: lshrv |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 |
| ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]] |
| ; MIPS32: $v0 = COPY [[LSHR]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = COPY $a1 |
| %2:_(s32) = G_LSHR %0, %1 |
| $v0 = COPY %2(s32) |
| RetRA implicit $v0 |
| |
| ... |