| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 |
| --- | |
| |
| define void @eq() {entry: ret void} |
| define void @ne() {entry: ret void} |
| define void @sgt() {entry: ret void} |
| define void @sge() {entry: ret void} |
| define void @slt() {entry: ret void} |
| define void @sle() {entry: ret void} |
| define void @ugt() {entry: ret void} |
| define void @uge() {entry: ret void} |
| define void @ult() {entry: ret void} |
| define void @ule() {entry: ret void} |
| |
| ... |
| --- |
| name: eq |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: eq |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]] |
| ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1 |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTiu]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ne |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ne |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]] |
| ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]] |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: sgt |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: sgt |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]] |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: sge |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: sge |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]] |
| ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1 |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: slt |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: slt |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]] |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: sle |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: sle |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]] |
| ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1 |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ugt |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ugt |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]] |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: uge |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: uge |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]] |
| ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1 |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ult |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ult |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]] |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ule |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ule |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 |
| ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]] |
| ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1 |
| ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1 |
| ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]] |
| ; MIPS32: $v0 = COPY [[AND]] |
| ; MIPS32: RetRA implicit $v0 |
| %0:gprb(s32) = COPY $a0 |
| %1:gprb(s32) = COPY $a1 |
| %4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1 |
| %5:gprb(s32) = G_CONSTANT i32 1 |
| %6:gprb(s32) = COPY %4(s32) |
| %3:gprb(s32) = G_AND %6, %5 |
| $v0 = COPY %3(s32) |
| RetRA implicit $v0 |
| |
| ... |