[TableGen] Add a non-default constructor to CodeGenSchedClass and use it via emplace_back to create new SchedClasses instead of using resize(size+1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328183 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index a21e44b..1f812fd 100644
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -557,10 +557,9 @@
void CodeGenSchedModels::collectSchedClasses() {
// NoItinerary is always the first class at Idx=0
- SchedClasses.resize(1);
- SchedClasses.back().Index = 0;
- SchedClasses.back().Name = "NoInstrModel";
- SchedClasses.back().ItinClassDef = Records.getDef("NoItinerary");
+ assert(SchedClasses.empty() && "Expected empty sched class");
+ SchedClasses.emplace_back(0, "NoInstrModel",
+ Records.getDef("NoItinerary"));
SchedClasses.back().ProcIndices.push_back(0);
// Create a SchedClass for each unique combination of itinerary class and
@@ -572,9 +571,7 @@
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
// ProcIdx == 0 indicates the class applies to all processors.
- IdxVec ProcIndices(1, 0);
-
- unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
+ unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
InstrClassMap[Inst->TheDef] = SCIdx;
}
// Create classes for InstRW defs.
@@ -716,11 +713,11 @@
return Idx;
}
Idx = SchedClasses.size();
- SchedClasses.resize(Idx+1);
+ SchedClasses.emplace_back(Idx,
+ createSchedClassName(ItinClassDef, OperWrites,
+ OperReads),
+ ItinClassDef);
CodeGenSchedClass &SC = SchedClasses.back();
- SC.Index = Idx;
- SC.Name = createSchedClassName(ItinClassDef, OperWrites, OperReads);
- SC.ItinClassDef = ItinClassDef;
SC.Writes = OperWrites;
SC.Reads = OperReads;
SC.ProcIndices = ProcIndices;
@@ -788,10 +785,8 @@
}
}
unsigned SCIdx = SchedClasses.size();
- SchedClasses.resize(SCIdx+1);
+ SchedClasses.emplace_back(SCIdx, createSchedClassName(InstDefs), nullptr);
CodeGenSchedClass &SC = SchedClasses.back();
- SC.Index = SCIdx;
- SC.Name = createSchedClassName(InstDefs);
DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on "
<< InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h
index 3265cfb..2d906bb 100644
--- a/utils/TableGen/CodeGenSchedule.h
+++ b/utils/TableGen/CodeGenSchedule.h
@@ -139,7 +139,8 @@
// off to join another inferred class.
RecVec InstRWs;
- CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
+ CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
+ : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
ArrayRef<unsigned> R) const {
@@ -198,9 +199,9 @@
// Per-operand machine model resources associated with this processor.
RecVec ProcResourceDefs;
- CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
+ CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
Record *IDef) :
- Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
+ Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef) {}
bool hasItineraries() const {
return !ItinsDef->getValueAsListOfDefs("IID").empty();