| //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| //===----------------------------------------------------------------------===// |
| // SVE Integer Arithmetic - Unpredicated Group |
| //===----------------------------------------------------------------------===// |
| |
| class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm, |
| ZPRRegOp zprty> |
| : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), |
| asm, "\t$Zd, $Zn, $Zm", |
| "", []>, Sched<[]> { |
| bits<5> Zd; |
| bits<5> Zm; |
| bits<5> Zn; |
| let Inst{31-24} = 0b00000100; |
| let Inst{23-22} = sz8_64; |
| let Inst{21} = 0b1; |
| let Inst{20-16} = Zm; |
| let Inst{15-13} = 0b000; |
| let Inst{12-10} = opc; |
| let Inst{9-5} = Zn; |
| let Inst{4-0} = Zd; |
| } |
| |
| multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> { |
| def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; |
| def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; |
| def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; |
| def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; |
| } |
