| //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file contains the RISCV implementation of the TargetRegisterInfo class. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "RISCVRegisterInfo.h" |
| #include "RISCV.h" |
| #include "RISCVSubtarget.h" |
| #include "llvm/CodeGen/MachineFrameInfo.h" |
| #include "llvm/CodeGen/MachineFunction.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/RegisterScavenging.h" |
| #include "llvm/Support/ErrorHandling.h" |
| #include "llvm/Target/TargetFrameLowering.h" |
| #include "llvm/Target/TargetInstrInfo.h" |
| |
| #define GET_REGINFO_TARGET_DESC |
| #include "RISCVGenRegisterInfo.inc" |
| |
| using namespace llvm; |
| |
| RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) |
| : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, |
| /*PC*/0, HwMode) {} |
| |
| const MCPhysReg * |
| RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
| return CSR_SaveList; |
| } |
| |
| BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| BitVector Reserved(getNumRegs()); |
| |
| // Use markSuperRegs to ensure any register aliases are also reserved |
| markSuperRegs(Reserved, RISCV::X0); // zero |
| markSuperRegs(Reserved, RISCV::X1); // ra |
| markSuperRegs(Reserved, RISCV::X2); // sp |
| markSuperRegs(Reserved, RISCV::X3); // gp |
| markSuperRegs(Reserved, RISCV::X4); // tp |
| markSuperRegs(Reserved, RISCV::X8); // fp |
| assert(checkAllSuperRegsMarked(Reserved)); |
| return Reserved; |
| } |
| |
| void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
| int SPAdj, unsigned FIOperandNum, |
| RegScavenger *RS) const { |
| report_fatal_error("Subroutines not supported yet"); |
| } |
| |
| unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
| return RISCV::X8; |
| } |