| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE |
| ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE |
| |
| define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4i32: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4i32: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.32 q1, q0 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 4, <4 x i1> %c) |
| ret void |
| } |
| |
| define arm_aapcs_vfpcc void @masked_v4i32_align1(<4 x i32> *%dest, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4i32_align1: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4i32_align1: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.32 q1, q0 |
| ; CHECK-BE-NEXT: vrev32.8 q0, q1 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 1, <4 x i1> %c) |
| ret void |
| } |
| |
| define i8* @masked_v4i32_pre(i8* %y, i8* %x, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4i32_pre: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4i32_pre: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.32 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <4 x i32>* |
| %1 = load <4 x i32>, <4 x i32>* %0, align 4 |
| %2 = bitcast i8* %z to <4 x i32>* |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c) |
| ret i8* %z |
| } |
| |
| define i8* @masked_v4i32_post(i8* %y, i8* %x, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4i32_post: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4i32_post: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.32 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <4 x i32>* |
| %1 = load <4 x i32>, <4 x i32>* %0, align 4 |
| %2 = bitcast i8* %y to <4 x i32>* |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c) |
| ret i8* %z |
| } |
| |
| |
| define arm_aapcs_vfpcc void @masked_v8i16(<8 x i16> *%dest, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8i16: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrht.16 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8i16: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.16 q1, q0 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q1, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 2, <8 x i1> %c) |
| ret void |
| } |
| |
| define arm_aapcs_vfpcc void @masked_v8i16_align1(<8 x i16> *%dest, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8i16_align1: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8i16_align1: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.16 q1, q0 |
| ; CHECK-BE-NEXT: vrev16.8 q0, q1 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q1, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 1, <8 x i1> %c) |
| ret void |
| } |
| |
| define i8* @masked_v8i16_pre(i8* %y, i8* %x, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8i16_pre: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8i16_pre: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrh.u16 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.16 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <8 x i16>* |
| %1 = load <8 x i16>, <8 x i16>* %0, align 4 |
| %2 = bitcast i8* %z to <8 x i16>* |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c) |
| ret i8* %z |
| } |
| |
| define i8* @masked_v8i16_post(i8* %y, i8* %x, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8i16_post: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8i16_post: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrh.u16 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.16 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <8 x i16>* |
| %1 = load <8 x i16>, <8 x i16>* %0, align 4 |
| %2 = bitcast i8* %y to <8 x i16>* |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c) |
| ret i8* %z |
| } |
| |
| |
| define arm_aapcs_vfpcc void @masked_v16i8(<16 x i8> *%dest, <16 x i8> %a) { |
| ; CHECK-LE-LABEL: masked_v16i8: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v16i8: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.8 q1, q0 |
| ; CHECK-BE-NEXT: vpt.s8 gt, q1, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q1, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <16 x i8> %a, zeroinitializer |
| call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %a, <16 x i8>* %dest, i32 1, <16 x i1> %c) |
| ret void |
| } |
| |
| define i8* @masked_v16i8_pre(i8* %y, i8* %x, <16 x i8> %a) { |
| ; CHECK-LE-LABEL: masked_v16i8_pre: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q1, [r0, #4] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v16i8_pre: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrb.u8 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.8 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q1, [r0, #4] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <16 x i8>* |
| %1 = load <16 x i8>, <16 x i8>* %0, align 4 |
| %2 = bitcast i8* %z to <16 x i8>* |
| %c = icmp sgt <16 x i8> %a, zeroinitializer |
| call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c) |
| ret i8* %z |
| } |
| |
| define i8* @masked_v16i8_post(i8* %y, i8* %x, <16 x i8> %a) { |
| ; CHECK-LE-LABEL: masked_v16i8_post: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q1, [r0] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v16i8_post: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrb.u8 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.8 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q1, [r0] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <16 x i8>* |
| %1 = load <16 x i8>, <16 x i8>* %0, align 4 |
| %2 = bitcast i8* %y to <16 x i8>* |
| %c = icmp sgt <16 x i8> %a, zeroinitializer |
| call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c) |
| ret i8* %z |
| } |
| |
| |
| define arm_aapcs_vfpcc void @masked_v4f32(<4 x float> *%dest, <4 x float> %a, <4 x i32> %b) { |
| ; CHECK-LE-LABEL: masked_v4f32: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.i32 ne, q1, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4f32: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.32 q2, q1 |
| ; CHECK-BE-NEXT: vrev64.32 q1, q0 |
| ; CHECK-BE-NEXT: vpt.i32 ne, q2, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp ugt <4 x i32> %b, zeroinitializer |
| call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 4, <4 x i1> %c) |
| ret void |
| } |
| |
| define arm_aapcs_vfpcc void @masked_v4f32_align1(<4 x float> *%dest, <4 x float> %a, <4 x i32> %b) { |
| ; CHECK-LE-LABEL: masked_v4f32_align1: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.i32 ne, q1, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4f32_align1: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.32 q2, q1 |
| ; CHECK-BE-NEXT: vrev64.32 q1, q0 |
| ; CHECK-BE-NEXT: vrev32.8 q0, q1 |
| ; CHECK-BE-NEXT: vpt.i32 ne, q2, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp ugt <4 x i32> %b, zeroinitializer |
| call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 1, <4 x i1> %c) |
| ret void |
| } |
| |
| define i8* @masked_v4f32_pre(i8* %y, i8* %x, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4f32_pre: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4f32_pre: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.32 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <4 x float>* |
| %1 = load <4 x float>, <4 x float>* %0, align 4 |
| %2 = bitcast i8* %z to <4 x float>* |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c) |
| ret i8* %z |
| } |
| |
| define i8* @masked_v4f32_post(i8* %y, i8* %x, <4 x i32> %a) { |
| ; CHECK-LE-LABEL: masked_v4f32_post: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v4f32_post: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.32 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrwt.32 q1, [r0] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <4 x float>* |
| %1 = load <4 x float>, <4 x float>* %0, align 4 |
| %2 = bitcast i8* %y to <4 x float>* |
| %c = icmp sgt <4 x i32> %a, zeroinitializer |
| call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c) |
| ret i8* %z |
| } |
| |
| |
| define arm_aapcs_vfpcc void @masked_v8f16(<8 x half> *%dest, <8 x half> %a, <8 x i16> %b) { |
| ; CHECK-LE-LABEL: masked_v8f16: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.i16 ne, q1, zr |
| ; CHECK-LE-NEXT: vstrht.16 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8f16: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.16 q2, q1 |
| ; CHECK-BE-NEXT: vrev64.16 q1, q0 |
| ; CHECK-BE-NEXT: vpt.i16 ne, q2, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp ugt <8 x i16> %b, zeroinitializer |
| call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 2, <8 x i1> %c) |
| ret void |
| } |
| |
| define arm_aapcs_vfpcc void @masked_v8f16_align1(<8 x half> *%dest, <8 x half> %a, <8 x i16> %b) { |
| ; CHECK-LE-LABEL: masked_v8f16_align1: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vpt.i16 ne, q1, zr |
| ; CHECK-LE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8f16_align1: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vrev64.16 q2, q0 |
| ; CHECK-BE-NEXT: vrev16.8 q0, q2 |
| ; CHECK-BE-NEXT: vrev64.16 q2, q1 |
| ; CHECK-BE-NEXT: vpt.i16 ne, q2, zr |
| ; CHECK-BE-NEXT: vstrbt.8 q0, [r0] |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp ugt <8 x i16> %b, zeroinitializer |
| call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 1, <8 x i1> %c) |
| ret void |
| } |
| |
| define i8* @masked_v8f16_pre(i8* %y, i8* %x, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8f16_pre: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8f16_pre: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrh.u16 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.16 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <8 x half>* |
| %1 = load <8 x half>, <8 x half>* %0, align 4 |
| %2 = bitcast i8* %z to <8 x half>* |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c) |
| ret i8* %z |
| } |
| |
| define i8* @masked_v8f16_post(i8* %y, i8* %x, <8 x i16> %a) { |
| ; CHECK-LE-LABEL: masked_v8f16_post: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: vldr d1, [sp] |
| ; CHECK-LE-NEXT: vldrw.u32 q1, [r1] |
| ; CHECK-LE-NEXT: vmov d0, r2, r3 |
| ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr |
| ; CHECK-LE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-LE-NEXT: adds r0, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v8f16_post: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: vldr d1, [sp] |
| ; CHECK-BE-NEXT: vldrh.u16 q1, [r1] |
| ; CHECK-BE-NEXT: vmov d0, r3, r2 |
| ; CHECK-BE-NEXT: vrev64.16 q2, q0 |
| ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr |
| ; CHECK-BE-NEXT: vstrht.16 q1, [r0] |
| ; CHECK-BE-NEXT: adds r0, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %z = getelementptr inbounds i8, i8* %y, i32 4 |
| %0 = bitcast i8* %x to <8 x half>* |
| %1 = load <8 x half>, <8 x half>* %0, align 4 |
| %2 = bitcast i8* %y to <8 x half>* |
| %c = icmp sgt <8 x i16> %a, zeroinitializer |
| call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c) |
| ret i8* %z |
| } |
| |
| |
| define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) { |
| ; CHECK-LE-LABEL: masked_v2i64: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: .pad #4 |
| ; CHECK-LE-NEXT: sub sp, #4 |
| ; CHECK-LE-NEXT: vmov r2, s0 |
| ; CHECK-LE-NEXT: movs r3, #0 |
| ; CHECK-LE-NEXT: vmov r1, s1 |
| ; CHECK-LE-NEXT: vmov r12, s3 |
| ; CHECK-LE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-LE-NEXT: vmov r2, s2 |
| ; CHECK-LE-NEXT: sbcs.w r1, r3, r1 |
| ; CHECK-LE-NEXT: mov.w r1, #0 |
| ; CHECK-LE-NEXT: it lt |
| ; CHECK-LE-NEXT: movlt r1, #1 |
| ; CHECK-LE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-LE-NEXT: sbcs.w r2, r3, r12 |
| ; CHECK-LE-NEXT: it lt |
| ; CHECK-LE-NEXT: movlt r3, #1 |
| ; CHECK-LE-NEXT: cmp r3, #0 |
| ; CHECK-LE-NEXT: it ne |
| ; CHECK-LE-NEXT: mvnne r3, #1 |
| ; CHECK-LE-NEXT: bfi r3, r1, #0, #1 |
| ; CHECK-LE-NEXT: and r1, r3, #3 |
| ; CHECK-LE-NEXT: lsls r2, r3, #31 |
| ; CHECK-LE-NEXT: it ne |
| ; CHECK-LE-NEXT: vstrne d0, [r0] |
| ; CHECK-LE-NEXT: lsls r1, r1, #30 |
| ; CHECK-LE-NEXT: it mi |
| ; CHECK-LE-NEXT: vstrmi d1, [r0, #8] |
| ; CHECK-LE-NEXT: add sp, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v2i64: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: .pad #4 |
| ; CHECK-BE-NEXT: sub sp, #4 |
| ; CHECK-BE-NEXT: vrev64.32 q1, q0 |
| ; CHECK-BE-NEXT: movs r3, #0 |
| ; CHECK-BE-NEXT: vmov r2, s7 |
| ; CHECK-BE-NEXT: vmov r1, s6 |
| ; CHECK-BE-NEXT: vmov r12, s4 |
| ; CHECK-BE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-BE-NEXT: vmov r2, s5 |
| ; CHECK-BE-NEXT: sbcs.w r1, r3, r1 |
| ; CHECK-BE-NEXT: mov.w r1, #0 |
| ; CHECK-BE-NEXT: it lt |
| ; CHECK-BE-NEXT: movlt r1, #1 |
| ; CHECK-BE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-BE-NEXT: sbcs.w r2, r3, r12 |
| ; CHECK-BE-NEXT: it lt |
| ; CHECK-BE-NEXT: movlt r3, #1 |
| ; CHECK-BE-NEXT: cmp r3, #0 |
| ; CHECK-BE-NEXT: it ne |
| ; CHECK-BE-NEXT: mvnne r3, #1 |
| ; CHECK-BE-NEXT: bfi r3, r1, #0, #1 |
| ; CHECK-BE-NEXT: and r1, r3, #3 |
| ; CHECK-BE-NEXT: lsls r2, r3, #31 |
| ; CHECK-BE-NEXT: it ne |
| ; CHECK-BE-NEXT: vstrne d0, [r0] |
| ; CHECK-BE-NEXT: lsls r1, r1, #30 |
| ; CHECK-BE-NEXT: it mi |
| ; CHECK-BE-NEXT: vstrmi d1, [r0, #8] |
| ; CHECK-BE-NEXT: add sp, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <2 x i64> %a, zeroinitializer |
| call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %a, <2 x i64>* %dest, i32 8, <2 x i1> %c) |
| ret void |
| } |
| |
| define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) { |
| ; CHECK-LE-LABEL: masked_v2f64: |
| ; CHECK-LE: @ %bb.0: @ %entry |
| ; CHECK-LE-NEXT: .pad #4 |
| ; CHECK-LE-NEXT: sub sp, #4 |
| ; CHECK-LE-NEXT: vmov r2, s4 |
| ; CHECK-LE-NEXT: movs r3, #0 |
| ; CHECK-LE-NEXT: vmov r1, s5 |
| ; CHECK-LE-NEXT: vmov r12, s7 |
| ; CHECK-LE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-LE-NEXT: vmov r2, s6 |
| ; CHECK-LE-NEXT: sbcs.w r1, r3, r1 |
| ; CHECK-LE-NEXT: mov.w r1, #0 |
| ; CHECK-LE-NEXT: it lt |
| ; CHECK-LE-NEXT: movlt r1, #1 |
| ; CHECK-LE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-LE-NEXT: sbcs.w r2, r3, r12 |
| ; CHECK-LE-NEXT: it lt |
| ; CHECK-LE-NEXT: movlt r3, #1 |
| ; CHECK-LE-NEXT: cmp r3, #0 |
| ; CHECK-LE-NEXT: it ne |
| ; CHECK-LE-NEXT: mvnne r3, #1 |
| ; CHECK-LE-NEXT: bfi r3, r1, #0, #1 |
| ; CHECK-LE-NEXT: and r1, r3, #3 |
| ; CHECK-LE-NEXT: lsls r2, r3, #31 |
| ; CHECK-LE-NEXT: it ne |
| ; CHECK-LE-NEXT: vstrne d0, [r0] |
| ; CHECK-LE-NEXT: lsls r1, r1, #30 |
| ; CHECK-LE-NEXT: it mi |
| ; CHECK-LE-NEXT: vstrmi d1, [r0, #8] |
| ; CHECK-LE-NEXT: add sp, #4 |
| ; CHECK-LE-NEXT: bx lr |
| ; |
| ; CHECK-BE-LABEL: masked_v2f64: |
| ; CHECK-BE: @ %bb.0: @ %entry |
| ; CHECK-BE-NEXT: .pad #4 |
| ; CHECK-BE-NEXT: sub sp, #4 |
| ; CHECK-BE-NEXT: vrev64.32 q2, q1 |
| ; CHECK-BE-NEXT: movs r3, #0 |
| ; CHECK-BE-NEXT: vmov r2, s11 |
| ; CHECK-BE-NEXT: vmov r1, s10 |
| ; CHECK-BE-NEXT: vmov r12, s8 |
| ; CHECK-BE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-BE-NEXT: vmov r2, s9 |
| ; CHECK-BE-NEXT: sbcs.w r1, r3, r1 |
| ; CHECK-BE-NEXT: mov.w r1, #0 |
| ; CHECK-BE-NEXT: it lt |
| ; CHECK-BE-NEXT: movlt r1, #1 |
| ; CHECK-BE-NEXT: rsbs r2, r2, #0 |
| ; CHECK-BE-NEXT: sbcs.w r2, r3, r12 |
| ; CHECK-BE-NEXT: it lt |
| ; CHECK-BE-NEXT: movlt r3, #1 |
| ; CHECK-BE-NEXT: cmp r3, #0 |
| ; CHECK-BE-NEXT: it ne |
| ; CHECK-BE-NEXT: mvnne r3, #1 |
| ; CHECK-BE-NEXT: bfi r3, r1, #0, #1 |
| ; CHECK-BE-NEXT: and r1, r3, #3 |
| ; CHECK-BE-NEXT: lsls r2, r3, #31 |
| ; CHECK-BE-NEXT: it ne |
| ; CHECK-BE-NEXT: vstrne d0, [r0] |
| ; CHECK-BE-NEXT: lsls r1, r1, #30 |
| ; CHECK-BE-NEXT: it mi |
| ; CHECK-BE-NEXT: vstrmi d1, [r0, #8] |
| ; CHECK-BE-NEXT: add sp, #4 |
| ; CHECK-BE-NEXT: bx lr |
| entry: |
| %c = icmp sgt <2 x i64> %b, zeroinitializer |
| call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %a, <2 x double>* %dest, i32 8, <2 x i1> %c) |
| ret void |
| } |
| |
| |
| declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>) |
| declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) |
| declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>) |
| declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) |
| declare void @llvm.masked.store.v8f16.p0v8f16(<8 x half>, <8 x half>*, i32, <8 x i1>) |
| declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>) |
| declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>) |